illumos/illumos-gate: usr/src/uts/i86pc/os/cpuid.c annotate

annotate usr/src/uts/i86pc/os/cpuid.c @ 14043:0291cd939b43

3506 Use "hypervisor" CPUID bit to detect hypervisor environment Reviewed by: Hans Rosenfeld <hans.rosenfeld@nexenta.com> Reviewed by: Albert Lee <trisk@nexenta.com> Approved by: Robert Mustacchi <rm@joyent.com>

author	Yuri Pankov <yuri.pankov@nexenta.com>
date	Mon, 10 Jun 2013 09:51:40 -0700
parents	b151bd260b71
children

rev	line source
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2 * CDDL HEADER START
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4 * The contents of this file are subject to the terms of the
1582 eb879d43ab47 6323525 Mutual exclusion primitives don't work as expected on Opteron systems kchow parents: 1414 diff changeset	5 * Common Development and Distribution License (the "License").
eb879d43ab47 6323525 Mutual exclusion primitives don't work as expected on Opteron systems kchow parents: 1414 diff changeset	6 * You may not use this file except in compliance with the License.
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	7 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	9 * or http://www.opensolaris.org/os/licensing.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	10 * See the License for the specific language governing permissions
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	11 * and limitations under the License.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	12 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	13 * When distributing Covered Code, include this CDDL HEADER in each
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	15 * If applicable, add the following below this CDDL HEADER, with the
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	16 * fields enclosed by brackets "[]" replaced with your own identifying
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	17 * information: Portions Copyright [yyyy] [name of copyright owner]
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	18 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	19 * CDDL HEADER END
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	20 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	21 /*
12090 2986679fe0b5 6941777 determine_platform needs to do a better job inside a Xen HVM guest Frank Van Der Linden <Frank.Vanderlinden@Sun.COM> parents: 12004 diff changeset	22 * Copyright (c) 2004, 2010, Oracle and/or its affiliates. All rights reserved.
13498 e702644ca141 1687 Race in determine_platform / get_hwenv causes multi-CPU VM hang at boot Matt Amdur <mba@delphix.com> parents: 13425 diff changeset	23 * Copyright (c) 2011 by Delphix. All rights reserved.
14043 0291cd939b43 3506 Use "hypervisor" CPUID bit to detect hypervisor environment Yuri Pankov <yuri.pankov@nexenta.com> parents: 13905 diff changeset	24 * Copyright 2013 Nexenta Systems, Inc. All rights reserved.
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	25 */
9283 2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	26 /*
13041 2ba2eec82e2a 6932990 Support for TSC deadline timer Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM> parents: 12838 diff changeset	27 * Copyright (c) 2010, Intel Corporation.
9283 2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	28 * All rights reserved.
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	29 */
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	30 /*
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	31 * Portions Copyright 2009 Advanced Micro Devices, Inc.
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	32 */
13425 8640246a3548 1347 isainfo should indicate presence of vmx/svm support Bryan Cantrill <bryan@joyent.com> parents: 13148 diff changeset	33 /*
13675 a9ae30c28ee4 2413 %ymm* need to be preserved on way through PLT Robert Mustacchi <rm@joyent.com> parents: 13655 diff changeset	34 * Copyright (c) 2012, Joyent, Inc. All rights reserved.
13425 8640246a3548 1347 isainfo should indicate presence of vmx/svm support Bryan Cantrill <bryan@joyent.com> parents: 13148 diff changeset	35 */
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	36 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	37 * Various routines to handle identification
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	38 * and classification of x86 processors.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	39 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	40
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	41 #include <sys/types.h>
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	42 #include <sys/archsystm.h>
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	43 #include <sys/x86_archext.h>
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	44 #include <sys/kmem.h>
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	45 #include <sys/systm.h>
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	46 #include <sys/cmn_err.h>
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	47 #include <sys/sunddi.h>
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	48 #include <sys/sunndi.h>
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	49 #include <sys/cpuvar.h>
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	50 #include <sys/processor.h>
5045 75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	51 #include <sys/sysmacros.h>
3434 5142e1d7d0bc 6461311 multi-level CMT scheduling optimizations esaxe parents: 2869 diff changeset	52 #include <sys/pg.h>
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	53 #include <sys/fp.h>
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	54 #include <sys/controlregs.h>
13148 67d1861e02c1 6970888 panic BAD TRAP: type=d (#gp General protection) due to incorrect use of x86_featureset Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13146 diff changeset	55 #include <sys/bitmap.h>
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	56 #include <sys/auxv_386.h>
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	57 #include <sys/memnode.h>
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	58 #include <sys/pci_cfgspace.h>
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	59
7532 bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	60 #ifdef __xpv
bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	61 #include <sys/hypervisor.h>
8930 02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	62 #else
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	63 #include <sys/ontrap.h>
7532 bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	64 #endif
bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	65
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	66 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	67 * Pass 0 of cpuid feature analysis happens in locore. It contains special code
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	68 * to recognize Cyrix processors that are not cpuid-compliant, and to deal with
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	69 * them accordingly. For most modern processors, feature detection occurs here
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	70 * in pass 1.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	71 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	72 * Pass 1 of cpuid feature analysis happens just at the beginning of mlsetup()
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	73 * for the boot CPU and does the basic analysis that the early kernel needs.
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	74 * x86_featureset is set based on the return value of cpuid_pass1() of the boot
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	75 * CPU.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	76 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	77 * Pass 1 includes:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	78 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	79 * o Determining vendor/model/family/stepping and setting x86_type and
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	80 * x86_vendor accordingly.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	81 * o Processing the feature flags returned by the cpuid instruction while
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	82 * applying any workarounds or tricks for the specific processor.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	83 * o Mapping the feature flags into Solaris feature bits (X86_*).
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	84 * o Processing extended feature flags if supported by the processor,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	85 * again while applying specific processor knowledge.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	86 * o Determining the CMT characteristics of the system.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	87 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	88 * Pass 1 is done on non-boot CPUs during their initialization and the results
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	89 * are used only as a meager attempt at ensuring that all processors within the
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	90 * system support the same features.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	91 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	92 * Pass 2 of cpuid feature analysis happens just at the beginning
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	93 * of startup(). It just copies in and corrects the remainder
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	94 * of the cpuid data we depend on: standard cpuid functions that we didn't
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	95 * need for pass1 feature analysis, and extended cpuid functions beyond the
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	96 * simple feature processing done in pass1.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	97 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	98 * Pass 3 of cpuid analysis is invoked after basic kernel services; in
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	99 * particular kernel memory allocation has been made available. It creates a
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	100 * readable brand string based on the data collected in the first two passes.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	101 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	102 * Pass 4 of cpuid analysis is invoked after post_startup() when all
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	103 * the support infrastructure for various hardware features has been
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	104 * initialized. It determines which processor features will be reported
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	105 * to userland via the aux vector.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	106 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	107 * All passes are executed on all CPUs, but only the boot CPU determines what
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	108 * features the kernel will use.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	109 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	110 * Much of the worst junk in this file is for the support of processors
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	111 * that didn't really implement the cpuid instruction properly.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	112 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	113 * NOTE: The accessor functions (cpuid_get*) are aware of, and ASSERT upon,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	114 * the pass numbers. Accordingly, changes to the pass code may require changes
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	115 * to the accessor code.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	116 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	117
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	118 uint_t x86_vendor = X86_VENDOR_IntelClone;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	119 uint_t x86_type = X86_TYPE_OTHER;
7589 7de800909a06 PSARC 2008/560 Intel IOMMU Vikram Hegde <Vikram.Hegde@Sun.COM> parents: 7532 diff changeset	120 uint_t x86_clflush_size = 0;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	121
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	122 uint_t pentiumpro_bug4046376;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	123 uint_t pentiumpro_bug4064495;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	124
13148 67d1861e02c1 6970888 panic BAD TRAP: type=d (#gp General protection) due to incorrect use of x86_featureset Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13146 diff changeset	125 uchar_t x86_featureset[BT_SIZEOFMAP(NUM_X86_FEATURES)];
67d1861e02c1 6970888 panic BAD TRAP: type=d (#gp General protection) due to incorrect use of x86_featureset Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13146 diff changeset	126
67d1861e02c1 6970888 panic BAD TRAP: type=d (#gp General protection) due to incorrect use of x86_featureset Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13146 diff changeset	127 static char *x86_feature_names[NUM_X86_FEATURES] = {
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	128 "lgpg",
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	129 "tsc",
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	130 "msr",
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	131 "mtrr",
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	132 "pge",
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	133 "de",
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	134 "cmov",
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	135 "mmx",
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	136 "mca",
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	137 "pae",
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	138 "cv8",
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	139 "pat",
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	140 "sep",
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	141 "sse",
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	142 "sse2",
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	143 "htt",
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	144 "asysc",
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	145 "nx",
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	146 "sse3",
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	147 "cx16",
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	148 "cmp",
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	149 "tscp",
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	150 "mwait",
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	151 "sse4a",
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	152 "cpuid",
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	153 "ssse3",
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	154 "sse4_1",
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	155 "sse4_2",
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	156 "1gpg",
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	157 "clfsh",
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	158 "64",
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	159 "aes",
13146 8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	160 "pclmulqdq",
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	161 "xsave",
13425 8640246a3548 1347 isainfo should indicate presence of vmx/svm support Bryan Cantrill <bryan@joyent.com> parents: 13148 diff changeset	162 "avx",
8640246a3548 1347 isainfo should indicate presence of vmx/svm support Bryan Cantrill <bryan@joyent.com> parents: 13148 diff changeset	163 "vmx",
13681 73253247f9e5 2650 AMD family 0x15 PG support Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13675 diff changeset	164 "svm",
13905 b151bd260b71 3414 Need a new word of AT_SUN_HWCAP bits Robert Mustacchi <rm@joyent.com> parents: 13681 diff changeset	165 "topoext",
b151bd260b71 3414 Need a new word of AT_SUN_HWCAP bits Robert Mustacchi <rm@joyent.com> parents: 13681 diff changeset	166 "f16c",
b151bd260b71 3414 Need a new word of AT_SUN_HWCAP bits Robert Mustacchi <rm@joyent.com> parents: 13681 diff changeset	167 "rdrand"
13425 8640246a3548 1347 isainfo should indicate presence of vmx/svm support Bryan Cantrill <bryan@joyent.com> parents: 13148 diff changeset	168 };
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	169
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	170 boolean_t
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	171 is_x86_feature(void *featureset, uint_t feature)
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	172 {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	173 ASSERT(feature < NUM_X86_FEATURES);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	174 return (BT_TEST((ulong_t *)featureset, feature));
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	175 }
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	176
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	177 void
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	178 add_x86_feature(void *featureset, uint_t feature)
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	179 {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	180 ASSERT(feature < NUM_X86_FEATURES);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	181 BT_SET((ulong_t *)featureset, feature);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	182 }
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	183
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	184 void
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	185 remove_x86_feature(void *featureset, uint_t feature)
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	186 {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	187 ASSERT(feature < NUM_X86_FEATURES);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	188 BT_CLEAR((ulong_t *)featureset, feature);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	189 }
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	190
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	191 boolean_t
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	192 compare_x86_featureset(void setA, void setB)
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	193 {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	194 /*
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	195 * We assume that the unused bits of the bitmap are always zero.
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	196 */
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	197 if (memcmp(setA, setB, BT_SIZEOFMAP(NUM_X86_FEATURES)) == 0) {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	198 return (B_TRUE);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	199 } else {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	200 return (B_FALSE);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	201 }
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	202 }
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	203
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	204 void
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	205 print_x86_featureset(void *featureset)
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	206 {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	207 uint_t i;
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	208
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	209 for (i = 0; i < NUM_X86_FEATURES; i++) {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	210 if (is_x86_feature(featureset, i)) {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	211 cmn_err(CE_CONT, "?x86_feature: %s\n",
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	212 x86_feature_names[i]);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	213 }
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	214 }
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	215 }
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	216
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	217 uint_t enable486;
13146 8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	218
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	219 static size_t xsave_state_size = 0;
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	220 uint64_t xsave_bv_all = (XFEATURE_LEGACY_FP \| XFEATURE_SSE);
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	221 boolean_t xsave_force_disable = B_FALSE;
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	222
8990 67ae112ecc4f 6621869 Solaris hangs on TSC calibration while powering on under VMware ESX Server Surya Prakki <Surya.Prakki@Sun.COM> parents: 8930 diff changeset	223 /*
14043 0291cd939b43 3506 Use "hypervisor" CPUID bit to detect hypervisor environment Yuri Pankov <yuri.pankov@nexenta.com> parents: 13905 diff changeset	224 * This is set to platform type we are running on.
8990 67ae112ecc4f 6621869 Solaris hangs on TSC calibration while powering on under VMware ESX Server Surya Prakki <Surya.Prakki@Sun.COM> parents: 8930 diff changeset	225 */
10175 dd9708d1f561 6849090 Need to synch with newer versions of Xen and associated tools Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 10080 diff changeset	226 static int platform_type = -1;
dd9708d1f561 6849090 Need to synch with newer versions of Xen and associated tools Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 10080 diff changeset	227
dd9708d1f561 6849090 Need to synch with newer versions of Xen and associated tools Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 10080 diff changeset	228 #if !defined(__xpv)
dd9708d1f561 6849090 Need to synch with newer versions of Xen and associated tools Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 10080 diff changeset	229 /*
dd9708d1f561 6849090 Need to synch with newer versions of Xen and associated tools Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 10080 diff changeset	230 * Variable to patch if hypervisor platform detection needs to be
dd9708d1f561 6849090 Need to synch with newer versions of Xen and associated tools Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 10080 diff changeset	231 * disabled (e.g. platform_type will always be HW_NATIVE if this is 0).
dd9708d1f561 6849090 Need to synch with newer versions of Xen and associated tools Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 10080 diff changeset	232 */
dd9708d1f561 6849090 Need to synch with newer versions of Xen and associated tools Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 10080 diff changeset	233 int enable_platform_detection = 1;
dd9708d1f561 6849090 Need to synch with newer versions of Xen and associated tools Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 10080 diff changeset	234 #endif
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	235
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	236 /*
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	237 * monitor/mwait info.
5045 75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	238 *
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	239 * size_actual and buf_actual are the real address and size allocated to get
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	240 * proper mwait_buf alignement. buf_actual and size_actual should be passed
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	241 * to kmem_free(). Currently kmem_alloc() and mwait happen to both use
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	242 * processor cache-line alignment, but this is not guarantied in the furture.
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	243 */
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	244 struct mwait_info {
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	245 size_t mon_min; /* min size to avoid missed wakeups */
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	246 size_t mon_max; /* size to avoid false wakeups */
5045 75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	247 size_t size_actual; /* size actually allocated */
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	248 void buf_actual; / memory actually allocated */
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	249 uint32_t support; /* processor support of monitor/mwait */
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	250 };
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	251
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	252 /*
13146 8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	253 * xsave/xrestor info.
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	254 *
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	255 * This structure contains HW feature bits and size of the xsave save area.
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	256 * Note: the kernel will use the maximum size required for all hardware
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	257 * features. It is not optimize for potential memory savings if features at
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	258 * the end of the save area are not enabled.
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	259 */
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	260 struct xsave_info {
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	261 uint32_t xsav_hw_features_low; /* Supported HW features */
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	262 uint32_t xsav_hw_features_high; /* Supported HW features */
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	263 size_t xsav_max_size; /* max size save area for HW features */
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	264 size_t ymm_size; /* AVX: size of ymm save area */
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	265 size_t ymm_offset; /* AVX: offset for ymm save area */
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	266 };
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	267
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	268
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	269 /*
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	270 * These constants determine how many of the elements of the
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	271 * cpuid we cache in the cpuid_info data structure; the
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	272 * remaining elements are accessible via the cpuid instruction.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	273 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	274
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	275 #define NMAX_CPI_STD 6 /* eax = 0 .. 5 */
13681 73253247f9e5 2650 AMD family 0x15 PG support Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13675 diff changeset	276 #define NMAX_CPI_EXTD 0x1f /* eax = 0x80000000 .. 0x8000001e */
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	277
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	278 /*
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	279 * Some terminology needs to be explained:
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	280 * - Socket: Something that can be plugged into a motherboard.
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	281 * - Package: Same as socket
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	282 * - Chip: Same as socket. Note that AMD's documentation uses term "chip"
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	283 * differently: there, chip is the same as processor node (below)
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	284 * - Processor node: Some AMD processors have more than one
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	285 * "subprocessor" embedded in a package. These subprocessors (nodes)
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	286 * are fully-functional processors themselves with cores, caches,
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	287 * memory controllers, PCI configuration spaces. They are connected
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	288 * inside the package with Hypertransport links. On single-node
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	289 * processors, processor node is equivalent to chip/socket/package.
13681 73253247f9e5 2650 AMD family 0x15 PG support Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13675 diff changeset	290 * - Compute Unit: Some AMD processors pair cores in "compute units" that
73253247f9e5 2650 AMD family 0x15 PG support Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13675 diff changeset	291 * share the FPU and the I$ and L2 caches.
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	292 */
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	293
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	294 struct cpuid_info {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	295 uint_t cpi_pass; /* last pass completed */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	296 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	297 * standard function information
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	298 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	299 uint_t cpi_maxeax; /* fn 0: %eax */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	300 char cpi_vendorstr[13]; /* fn 0: %ebx:%ecx:%edx */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	301 uint_t cpi_vendor; /* enum of cpi_vendorstr */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	302
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	303 uint_t cpi_family; /* fn 1: extended family */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	304 uint_t cpi_model; /* fn 1: extended model */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	305 uint_t cpi_step; /* fn 1: stepping */
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	306 chipid_t cpi_chipid; /* fn 1: %ebx: Intel: chip # */
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	307 /* AMD: package/socket # */
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	308 uint_t cpi_brandid; /* fn 1: %ebx: brand ID */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	309 int cpi_clogid; /* fn 1: %ebx: thread # */
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	310 uint_t cpi_ncpu_per_chip; /* fn 1: %ebx: logical cpu count */
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	311 uint8_t cpi_cacheinfo[16]; /* fn 2: intel-style cache desc */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	312 uint_t cpi_ncache; /* fn 2: number of elements */
4606 ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	313 uint_t cpi_ncpu_shr_last_cache; /* fn 4: %eax: ncpus sharing cache */
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	314 id_t cpi_last_lvl_cacheid; /* fn 4: %eax: derived cache id */
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	315 uint_t cpi_std_4_size; /* fn 4: number of fn 4 elements */
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	316 struct cpuid_regs *cpi_std_4; / fn 4: %ecx == 0 .. fn4_size */
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	317 struct cpuid_regs cpi_std[NMAX_CPI_STD]; /* 0 .. 5 */
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	318 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	319 * extended function information
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	320 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	321 uint_t cpi_xmaxeax; /* fn 0x80000000: %eax */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	322 char cpi_brandstr[49]; /* fn 0x8000000[234] */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	323 uint8_t cpi_pabits; /* fn 0x80000006: %eax */
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	324 uint8_t cpi_vabits; /* fn 0x80000006: %eax */
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	325 struct cpuid_regs cpi_extd[NMAX_CPI_EXTD]; /* 0x800000XX */
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	326
5870 2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	327 id_t cpi_coreid; /* same coreid => strands share core */
2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	328 int cpi_pkgcoreid; /* core number within single package */
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	329 uint_t cpi_ncore_per_chip; /* AMD: fn 0x80000008: %ecx[7-0] */
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	330 /* Intel: fn 4: %eax[31-26] */
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	331 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	332 * supported feature information
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	333 */
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	334 uint32_t cpi_support[5];
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	335 #define STD_EDX_FEATURES 0
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	336 #define AMD_EDX_FEATURES 1
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	337 #define TM_EDX_FEATURES 2
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	338 #define STD_ECX_FEATURES 3
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	339 #define AMD_ECX_FEATURES 4
2869 324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	340 /*
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	341 * Synthesized information, where known.
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	342 */
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	343 uint32_t cpi_chiprev; /* See X86_CHIPREV_* in x86_archext.h */
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	344 const char cpi_chiprevstr; / May be NULL if chiprev unknown */
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	345 uint32_t cpi_socket; /* Chip package/socket type */
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	346
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	347 struct mwait_info cpi_mwait; /* fn 5: monitor/mwait info */
7282 5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	348 uint32_t cpi_apicid;
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	349 uint_t cpi_procnodeid; /* AMD: nodeID on HT, Intel: chipid */
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	350 uint_t cpi_procnodes_per_pkg; /* AMD: # of nodes in the package */
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	351 /* Intel: 1 */
13681 73253247f9e5 2650 AMD family 0x15 PG support Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13675 diff changeset	352 uint_t cpi_compunitid; /* AMD: ComputeUnit ID, Intel: coreid */
73253247f9e5 2650 AMD family 0x15 PG support Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13675 diff changeset	353 uint_t cpi_cores_per_compunit; /* AMD: # of cores in the ComputeUnit */
13146 8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	354
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	355 struct xsave_info cpi_xsave; /* fn D: xsave/xrestor info */
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	356 };
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	357
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	358
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	359 static struct cpuid_info cpuid_info0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	360
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	361 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	362 * These bit fields are defined by the Intel Application Note AP-485
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	363 * "Intel Processor Identification and the CPUID Instruction"
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	364 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	365 #define CPI_FAMILY_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 27, 20)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	366 #define CPI_MODEL_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 19, 16)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	367 #define CPI_TYPE(cpi) BITX((cpi)->cpi_std[1].cp_eax, 13, 12)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	368 #define CPI_FAMILY(cpi) BITX((cpi)->cpi_std[1].cp_eax, 11, 8)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	369 #define CPI_STEP(cpi) BITX((cpi)->cpi_std[1].cp_eax, 3, 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	370 #define CPI_MODEL(cpi) BITX((cpi)->cpi_std[1].cp_eax, 7, 4)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	371
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	372 #define CPI_FEATURES_EDX(cpi) ((cpi)->cpi_std[1].cp_edx)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	373 #define CPI_FEATURES_ECX(cpi) ((cpi)->cpi_std[1].cp_ecx)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	374 #define CPI_FEATURES_XTD_EDX(cpi) ((cpi)->cpi_extd[1].cp_edx)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	375 #define CPI_FEATURES_XTD_ECX(cpi) ((cpi)->cpi_extd[1].cp_ecx)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	376
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	377 #define CPI_BRANDID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 7, 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	378 #define CPI_CHUNKS(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 15, 7)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	379 #define CPI_CPU_COUNT(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 23, 16)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	380 #define CPI_APIC_ID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 31, 24)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	381
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	382 #define CPI_MAXEAX_MAX 0x100 /* sanity control */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	383 #define CPI_XMAXEAX_MAX 0x80000100
4606 ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	384 #define CPI_FN4_ECX_MAX 0x20 /* sanity: max fn 4 levels */
7282 5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	385 #define CPI_FNB_ECX_MAX 0x20 /* sanity: max fn B levels */
4606 ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	386
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	387 /*
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	388 * Function 4 (Deterministic Cache Parameters) macros
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	389 * Defined by Intel Application Note AP-485
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	390 */
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	391 #define CPI_NUM_CORES(regs) BITX((regs)->cp_eax, 31, 26)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	392 #define CPI_NTHR_SHR_CACHE(regs) BITX((regs)->cp_eax, 25, 14)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	393 #define CPI_FULL_ASSOC_CACHE(regs) BITX((regs)->cp_eax, 9, 9)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	394 #define CPI_SELF_INIT_CACHE(regs) BITX((regs)->cp_eax, 8, 8)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	395 #define CPI_CACHE_LVL(regs) BITX((regs)->cp_eax, 7, 5)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	396 #define CPI_CACHE_TYPE(regs) BITX((regs)->cp_eax, 4, 0)
7282 5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	397 #define CPI_CPU_LEVEL_TYPE(regs) BITX((regs)->cp_ecx, 15, 8)
4606 ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	398
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	399 #define CPI_CACHE_WAYS(regs) BITX((regs)->cp_ebx, 31, 22)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	400 #define CPI_CACHE_PARTS(regs) BITX((regs)->cp_ebx, 21, 12)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	401 #define CPI_CACHE_COH_LN_SZ(regs) BITX((regs)->cp_ebx, 11, 0)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	402
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	403 #define CPI_CACHE_SETS(regs) BITX((regs)->cp_ecx, 31, 0)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	404
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	405 #define CPI_PREFCH_STRIDE(regs) BITX((regs)->cp_edx, 9, 0)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	406
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	407
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	408 /*
1975 7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	409 * A couple of shorthand macros to identify "later" P6-family chips
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	410 * like the Pentium M and Core. First, the "older" P6-based stuff
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	411 * (loosely defined as "pre-Pentium-4"):
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	412 * P6, PII, Mobile PII, PII Xeon, PIII, Mobile PIII, PIII Xeon
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	413 */
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	414
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	415 #define IS_LEGACY_P6(cpi) ( \
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	416 cpi->cpi_family == 6 && \
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	417 (cpi->cpi_model == 1 \|\| \
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	418 cpi->cpi_model == 3 \|\| \
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	419 cpi->cpi_model == 5 \|\| \
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	420 cpi->cpi_model == 6 \|\| \
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	421 cpi->cpi_model == 7 \|\| \
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	422 cpi->cpi_model == 8 \|\| \
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	423 cpi->cpi_model == 0xA \|\| \
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	424 cpi->cpi_model == 0xB) \
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	425 )
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	426
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	427 /* A "new F6" is everything with family 6 that's not the above */
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	428 #define IS_NEW_F6(cpi) ((cpi->cpi_family == 6) && !IS_LEGACY_P6(cpi))
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	429
4855 3319ad80f260 6574102 Need to add extended family/model/stepping info to cpuid_pass1() for Intel processors ksadhukh parents: 4797 diff changeset	430 /* Extended family/model support */
3319ad80f260 6574102 Need to add extended family/model/stepping info to cpuid_pass1() for Intel processors ksadhukh parents: 4797 diff changeset	431 #define IS_EXTENDED_MODEL_INTEL(cpi) (cpi->cpi_family == 0x6 \|\| \
3319ad80f260 6574102 Need to add extended family/model/stepping info to cpuid_pass1() for Intel processors ksadhukh parents: 4797 diff changeset	432 cpi->cpi_family >= 0xf)
3319ad80f260 6574102 Need to add extended family/model/stepping info to cpuid_pass1() for Intel processors ksadhukh parents: 4797 diff changeset	433
1975 7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	434 /*
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	435 * Info for monitor/mwait idle loop.
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	436 *
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	437 * See cpuid section of "Intel 64 and IA-32 Architectures Software Developer's
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	438 * Manual Volume 2A: Instruction Set Reference, A-M" #25366-022US, November
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	439 * 2006.
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	440 * See MONITOR/MWAIT section of "AMD64 Architecture Programmer's Manual
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	441 * Documentation Updates" #33633, Rev 2.05, December 2006.
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	442 */
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	443 #define MWAIT_SUPPORT (0x00000001) /* mwait supported */
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	444 #define MWAIT_EXTENSIONS (0x00000002) /* extenstion supported */
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	445 #define MWAIT_ECX_INT_ENABLE (0x00000004) /* ecx 1 extension supported */
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	446 #define MWAIT_SUPPORTED(cpi) ((cpi)->cpi_std[1].cp_ecx & CPUID_INTC_ECX_MON)
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	447 #define MWAIT_INT_ENABLE(cpi) ((cpi)->cpi_std[5].cp_ecx & 0x2)
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	448 #define MWAIT_EXTENSION(cpi) ((cpi)->cpi_std[5].cp_ecx & 0x1)
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	449 #define MWAIT_SIZE_MIN(cpi) BITX((cpi)->cpi_std[5].cp_eax, 15, 0)
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	450 #define MWAIT_SIZE_MAX(cpi) BITX((cpi)->cpi_std[5].cp_ebx, 15, 0)
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	451 /*
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	452 * Number of sub-cstates for a given c-state.
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	453 */
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	454 #define MWAIT_NUM_SUBC_STATES(cpi, c_state) \
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	455 BITX((cpi)->cpi_std[5].cp_edx, c_state + 3, c_state)
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	456
7532 bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	457 /*
13146 8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	458 * XSAVE leaf 0xD enumeration
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	459 */
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	460 #define CPUID_LEAFD_2_YMM_OFFSET 576
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	461 #define CPUID_LEAFD_2_YMM_SIZE 256
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	462
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	463 /*
7532 bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	464 * Functions we consune from cpuid_subr.c; don't publish these in a header
bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	465 * file to try and keep people using the expected cpuid_* interfaces.
bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	466 */
bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	467 extern uint32_t _cpuid_skt(uint_t, uint_t, uint_t, uint_t);
9482 42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	468 extern const char *_cpuid_sktstr(uint_t, uint_t, uint_t, uint_t);
7532 bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	469 extern uint32_t _cpuid_chiprev(uint_t, uint_t, uint_t, uint_t);
bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	470 extern const char *_cpuid_chiprevstr(uint_t, uint_t, uint_t, uint_t);
bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	471 extern uint_t _cpuid_vendorstr_to_vendorcode(char *);
2869 324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	472
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	473 /*
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	474 * Apply up various platform-dependent restrictions where the
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	475 * underlying platform restrictions mean the CPU can be marked
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	476 * as less capable than its cpuid instruction would imply.
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	477 */
5084 7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	478 #if defined(__xpv)
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	479 static void
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	480 platform_cpuid_mangle(uint_t vendor, uint32_t eax, struct cpuid_regs *cp)
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	481 {
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	482 switch (eax) {
7532 bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	483 case 1: {
bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	484 uint32_t mcamask = DOMAIN_IS_INITDOMAIN(xen_info) ?
bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	485 0 : CPUID_INTC_EDX_MCA;
5084 7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	486 cp->cp_edx &=
7532 bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	487 ~(mcamask \|
bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	488 CPUID_INTC_EDX_PSE \|
5084 7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	489 CPUID_INTC_EDX_VME \| CPUID_INTC_EDX_DE \|
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	490 CPUID_INTC_EDX_SEP \| CPUID_INTC_EDX_MTRR \|
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	491 CPUID_INTC_EDX_PGE \| CPUID_INTC_EDX_PAT \|
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	492 CPUID_AMD_EDX_SYSC \| CPUID_INTC_EDX_SEP \|
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	493 CPUID_INTC_EDX_PSE36 \| CPUID_INTC_EDX_HTT);
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	494 break;
7532 bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	495 }
5084 7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	496
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	497 case 0x80000001:
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	498 cp->cp_edx &=
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	499 ~(CPUID_AMD_EDX_PSE \|
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	500 CPUID_INTC_EDX_VME \| CPUID_INTC_EDX_DE \|
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	501 CPUID_AMD_EDX_MTRR \| CPUID_AMD_EDX_PGE \|
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	502 CPUID_AMD_EDX_PAT \| CPUID_AMD_EDX_PSE36 \|
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	503 CPUID_AMD_EDX_SYSC \| CPUID_INTC_EDX_SEP \|
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	504 CPUID_AMD_EDX_TSCP);
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	505 cp->cp_ecx &= ~CPUID_AMD_ECX_CMP_LGCY;
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	506 break;
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	507 default:
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	508 break;
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	509 }
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	510
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	511 switch (vendor) {
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	512 case X86_VENDOR_Intel:
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	513 switch (eax) {
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	514 case 4:
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	515 /*
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	516 * Zero out the (ncores-per-chip - 1) field
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	517 */
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	518 cp->cp_eax &= 0x03fffffff;
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	519 break;
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	520 default:
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	521 break;
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	522 }
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	523 break;
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	524 case X86_VENDOR_AMD:
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	525 switch (eax) {
10080 29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	526
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	527 case 0x80000001:
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	528 cp->cp_ecx &= ~CPUID_AMD_ECX_CR8D;
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	529 break;
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	530
5084 7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	531 case 0x80000008:
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	532 /*
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	533 * Zero out the (ncores-per-chip - 1) field
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	534 */
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	535 cp->cp_ecx &= 0xffffff00;
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	536 break;
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	537 default:
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	538 break;
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	539 }
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	540 break;
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	541 default:
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	542 break;
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	543 }
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	544 }
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	545 #else
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	546 #define platform_cpuid_mangle(vendor, eax, cp) /* nothing */
5084 7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	547 #endif
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	548
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	549 /*
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	550 * Some undocumented ways of patching the results of the cpuid
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	551 * instruction to permit running Solaris 10 on future cpus that
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	552 * we don't currently support. Could be set to non-zero values
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	553 * via settings in eeprom.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	554 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	555
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	556 uint32_t cpuid_feature_ecx_include;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	557 uint32_t cpuid_feature_ecx_exclude;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	558 uint32_t cpuid_feature_edx_include;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	559 uint32_t cpuid_feature_edx_exclude;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	560
12004 93f274d4a367 PSARC/2009/104 Hot-Plug Support for ACPI-based Systems Gerry Liu <jiang.liu@intel.com> parents: 11919 diff changeset	561 /*
93f274d4a367 PSARC/2009/104 Hot-Plug Support for ACPI-based Systems Gerry Liu <jiang.liu@intel.com> parents: 11919 diff changeset	562 * Allocate space for mcpu_cpi in the machcpu structure for all non-boot CPUs.
93f274d4a367 PSARC/2009/104 Hot-Plug Support for ACPI-based Systems Gerry Liu <jiang.liu@intel.com> parents: 11919 diff changeset	563 */
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	564 void
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	565 cpuid_alloc_space(cpu_t *cpu)
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	566 {
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	567 /*
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	568 * By convention, cpu0 is the boot cpu, which is set up
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	569 * before memory allocation is available. All other cpus get
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	570 * their cpuid_info struct allocated here.
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	571 */
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	572 ASSERT(cpu->cpu_id != 0);
12004 93f274d4a367 PSARC/2009/104 Hot-Plug Support for ACPI-based Systems Gerry Liu <jiang.liu@intel.com> parents: 11919 diff changeset	573 ASSERT(cpu->cpu_m.mcpu_cpi == NULL);
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	574 cpu->cpu_m.mcpu_cpi =
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	575 kmem_zalloc(sizeof (*cpu->cpu_m.mcpu_cpi), KM_SLEEP);
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	576 }
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	577
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	578 void
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	579 cpuid_free_space(cpu_t *cpu)
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	580 {
4606 ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	581 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	582 int i;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	583
12004 93f274d4a367 PSARC/2009/104 Hot-Plug Support for ACPI-based Systems Gerry Liu <jiang.liu@intel.com> parents: 11919 diff changeset	584 ASSERT(cpi != NULL);
93f274d4a367 PSARC/2009/104 Hot-Plug Support for ACPI-based Systems Gerry Liu <jiang.liu@intel.com> parents: 11919 diff changeset	585 ASSERT(cpi != &cpuid_info0);
4606 ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	586
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	587 /*
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	588 * Free up any function 4 related dynamic storage
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	589 */
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	590 for (i = 1; i < cpi->cpi_std_4_size; i++)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	591 kmem_free(cpi->cpi_std_4[i], sizeof (struct cpuid_regs));
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	592 if (cpi->cpi_std_4_size > 0)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	593 kmem_free(cpi->cpi_std_4,
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	594 cpi->cpi_std_4_size * sizeof (struct cpuid_regs *));
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	595
12004 93f274d4a367 PSARC/2009/104 Hot-Plug Support for ACPI-based Systems Gerry Liu <jiang.liu@intel.com> parents: 11919 diff changeset	596 kmem_free(cpi, sizeof (*cpi));
93f274d4a367 PSARC/2009/104 Hot-Plug Support for ACPI-based Systems Gerry Liu <jiang.liu@intel.com> parents: 11919 diff changeset	597 cpu->cpu_m.mcpu_cpi = NULL;
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	598 }
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	599
5741 58423876d513 PSARC 2007/664 Paravirtualized Drivers for Fully Virtualized xVM Domains mrj parents: 5438 diff changeset	600 #if !defined(__xpv)
13498 e702644ca141 1687 Race in determine_platform / get_hwenv causes multi-CPU VM hang at boot Matt Amdur <mba@delphix.com> parents: 13425 diff changeset	601 /*
e702644ca141 1687 Race in determine_platform / get_hwenv causes multi-CPU VM hang at boot Matt Amdur <mba@delphix.com> parents: 13425 diff changeset	602 * Determine the type of the underlying platform. This is used to customize
e702644ca141 1687 Race in determine_platform / get_hwenv causes multi-CPU VM hang at boot Matt Amdur <mba@delphix.com> parents: 13425 diff changeset	603 * initialization of various subsystems (e.g. TSC). determine_platform() must
e702644ca141 1687 Race in determine_platform / get_hwenv causes multi-CPU VM hang at boot Matt Amdur <mba@delphix.com> parents: 13425 diff changeset	604 * only ever be called once to prevent two processors from seeing different
14043 0291cd939b43 3506 Use "hypervisor" CPUID bit to detect hypervisor environment Yuri Pankov <yuri.pankov@nexenta.com> parents: 13905 diff changeset	605 * values of platform_type. Must be called before cpuid_pass1(), the earliest
0291cd939b43 3506 Use "hypervisor" CPUID bit to detect hypervisor environment Yuri Pankov <yuri.pankov@nexenta.com> parents: 13905 diff changeset	606 * consumer to execute (uses _cpuid_chiprev --> synth_amd_info --> get_hwenv).
13498 e702644ca141 1687 Race in determine_platform / get_hwenv causes multi-CPU VM hang at boot Matt Amdur <mba@delphix.com> parents: 13425 diff changeset	607 */
e702644ca141 1687 Race in determine_platform / get_hwenv causes multi-CPU VM hang at boot Matt Amdur <mba@delphix.com> parents: 13425 diff changeset	608 void
e702644ca141 1687 Race in determine_platform / get_hwenv causes multi-CPU VM hang at boot Matt Amdur <mba@delphix.com> parents: 13425 diff changeset	609 determine_platform(void)
5741 58423876d513 PSARC 2007/664 Paravirtualized Drivers for Fully Virtualized xVM Domains mrj parents: 5438 diff changeset	610 {
58423876d513 PSARC 2007/664 Paravirtualized Drivers for Fully Virtualized xVM Domains mrj parents: 5438 diff changeset	611 struct cpuid_regs cp;
14043 0291cd939b43 3506 Use "hypervisor" CPUID bit to detect hypervisor environment Yuri Pankov <yuri.pankov@nexenta.com> parents: 13905 diff changeset	612 uint32_t base;
0291cd939b43 3506 Use "hypervisor" CPUID bit to detect hypervisor environment Yuri Pankov <yuri.pankov@nexenta.com> parents: 13905 diff changeset	613 uint32_t regs[4];
0291cd939b43 3506 Use "hypervisor" CPUID bit to detect hypervisor environment Yuri Pankov <yuri.pankov@nexenta.com> parents: 13905 diff changeset	614 char hvstr = (char )regs;
5741 58423876d513 PSARC 2007/664 Paravirtualized Drivers for Fully Virtualized xVM Domains mrj parents: 5438 diff changeset	615
13498 e702644ca141 1687 Race in determine_platform / get_hwenv causes multi-CPU VM hang at boot Matt Amdur <mba@delphix.com> parents: 13425 diff changeset	616 ASSERT(platform_type == -1);
e702644ca141 1687 Race in determine_platform / get_hwenv causes multi-CPU VM hang at boot Matt Amdur <mba@delphix.com> parents: 13425 diff changeset	617
10175 dd9708d1f561 6849090 Need to synch with newer versions of Xen and associated tools Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 10080 diff changeset	618 platform_type = HW_NATIVE;
dd9708d1f561 6849090 Need to synch with newer versions of Xen and associated tools Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 10080 diff changeset	619
dd9708d1f561 6849090 Need to synch with newer versions of Xen and associated tools Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 10080 diff changeset	620 if (!enable_platform_detection)
dd9708d1f561 6849090 Need to synch with newer versions of Xen and associated tools Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 10080 diff changeset	621 return;
dd9708d1f561 6849090 Need to synch with newer versions of Xen and associated tools Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 10080 diff changeset	622
5741 58423876d513 PSARC 2007/664 Paravirtualized Drivers for Fully Virtualized xVM Domains mrj parents: 5438 diff changeset	623 /*
14043 0291cd939b43 3506 Use "hypervisor" CPUID bit to detect hypervisor environment Yuri Pankov <yuri.pankov@nexenta.com> parents: 13905 diff changeset	624 * If Hypervisor CPUID bit is set, try to determine hypervisor
0291cd939b43 3506 Use "hypervisor" CPUID bit to detect hypervisor environment Yuri Pankov <yuri.pankov@nexenta.com> parents: 13905 diff changeset	625 * vendor signature, and set platform type accordingly.
0291cd939b43 3506 Use "hypervisor" CPUID bit to detect hypervisor environment Yuri Pankov <yuri.pankov@nexenta.com> parents: 13905 diff changeset	626 *
0291cd939b43 3506 Use "hypervisor" CPUID bit to detect hypervisor environment Yuri Pankov <yuri.pankov@nexenta.com> parents: 13905 diff changeset	627 * References:
0291cd939b43 3506 Use "hypervisor" CPUID bit to detect hypervisor environment Yuri Pankov <yuri.pankov@nexenta.com> parents: 13905 diff changeset	628 * http://lkml.org/lkml/2008/10/1/246
0291cd939b43 3506 Use "hypervisor" CPUID bit to detect hypervisor environment Yuri Pankov <yuri.pankov@nexenta.com> parents: 13905 diff changeset	629 * http://kb.vmware.com/kb/1009458
0291cd939b43 3506 Use "hypervisor" CPUID bit to detect hypervisor environment Yuri Pankov <yuri.pankov@nexenta.com> parents: 13905 diff changeset	630 */
0291cd939b43 3506 Use "hypervisor" CPUID bit to detect hypervisor environment Yuri Pankov <yuri.pankov@nexenta.com> parents: 13905 diff changeset	631 cp.cp_eax = 0x1;
0291cd939b43 3506 Use "hypervisor" CPUID bit to detect hypervisor environment Yuri Pankov <yuri.pankov@nexenta.com> parents: 13905 diff changeset	632 (void) __cpuid_insn(&cp);
0291cd939b43 3506 Use "hypervisor" CPUID bit to detect hypervisor environment Yuri Pankov <yuri.pankov@nexenta.com> parents: 13905 diff changeset	633 if ((cp.cp_ecx & CPUID_INTC_ECX_HV) != 0) {
0291cd939b43 3506 Use "hypervisor" CPUID bit to detect hypervisor environment Yuri Pankov <yuri.pankov@nexenta.com> parents: 13905 diff changeset	634 cp.cp_eax = 0x40000000;
0291cd939b43 3506 Use "hypervisor" CPUID bit to detect hypervisor environment Yuri Pankov <yuri.pankov@nexenta.com> parents: 13905 diff changeset	635 (void) __cpuid_insn(&cp);
0291cd939b43 3506 Use "hypervisor" CPUID bit to detect hypervisor environment Yuri Pankov <yuri.pankov@nexenta.com> parents: 13905 diff changeset	636 regs[0] = cp.cp_ebx;
0291cd939b43 3506 Use "hypervisor" CPUID bit to detect hypervisor environment Yuri Pankov <yuri.pankov@nexenta.com> parents: 13905 diff changeset	637 regs[1] = cp.cp_ecx;
0291cd939b43 3506 Use "hypervisor" CPUID bit to detect hypervisor environment Yuri Pankov <yuri.pankov@nexenta.com> parents: 13905 diff changeset	638 regs[2] = cp.cp_edx;
0291cd939b43 3506 Use "hypervisor" CPUID bit to detect hypervisor environment Yuri Pankov <yuri.pankov@nexenta.com> parents: 13905 diff changeset	639 regs[3] = 0;
0291cd939b43 3506 Use "hypervisor" CPUID bit to detect hypervisor environment Yuri Pankov <yuri.pankov@nexenta.com> parents: 13905 diff changeset	640 if (strcmp(hvstr, HVSIG_XEN_HVM) == 0) {
0291cd939b43 3506 Use "hypervisor" CPUID bit to detect hypervisor environment Yuri Pankov <yuri.pankov@nexenta.com> parents: 13905 diff changeset	641 platform_type = HW_XEN_HVM;
0291cd939b43 3506 Use "hypervisor" CPUID bit to detect hypervisor environment Yuri Pankov <yuri.pankov@nexenta.com> parents: 13905 diff changeset	642 return;
0291cd939b43 3506 Use "hypervisor" CPUID bit to detect hypervisor environment Yuri Pankov <yuri.pankov@nexenta.com> parents: 13905 diff changeset	643 }
0291cd939b43 3506 Use "hypervisor" CPUID bit to detect hypervisor environment Yuri Pankov <yuri.pankov@nexenta.com> parents: 13905 diff changeset	644 if (strcmp(hvstr, HVSIG_VMWARE) == 0) {
0291cd939b43 3506 Use "hypervisor" CPUID bit to detect hypervisor environment Yuri Pankov <yuri.pankov@nexenta.com> parents: 13905 diff changeset	645 platform_type = HW_VMWARE;
0291cd939b43 3506 Use "hypervisor" CPUID bit to detect hypervisor environment Yuri Pankov <yuri.pankov@nexenta.com> parents: 13905 diff changeset	646 return;
0291cd939b43 3506 Use "hypervisor" CPUID bit to detect hypervisor environment Yuri Pankov <yuri.pankov@nexenta.com> parents: 13905 diff changeset	647 }
0291cd939b43 3506 Use "hypervisor" CPUID bit to detect hypervisor environment Yuri Pankov <yuri.pankov@nexenta.com> parents: 13905 diff changeset	648 if (strcmp(hvstr, HVSIG_KVM) == 0) {
0291cd939b43 3506 Use "hypervisor" CPUID bit to detect hypervisor environment Yuri Pankov <yuri.pankov@nexenta.com> parents: 13905 diff changeset	649 platform_type = HW_KVM;
0291cd939b43 3506 Use "hypervisor" CPUID bit to detect hypervisor environment Yuri Pankov <yuri.pankov@nexenta.com> parents: 13905 diff changeset	650 return;
0291cd939b43 3506 Use "hypervisor" CPUID bit to detect hypervisor environment Yuri Pankov <yuri.pankov@nexenta.com> parents: 13905 diff changeset	651 }
0291cd939b43 3506 Use "hypervisor" CPUID bit to detect hypervisor environment Yuri Pankov <yuri.pankov@nexenta.com> parents: 13905 diff changeset	652 if (strcmp(hvstr, HVSIG_MICROSOFT) == 0)
0291cd939b43 3506 Use "hypervisor" CPUID bit to detect hypervisor environment Yuri Pankov <yuri.pankov@nexenta.com> parents: 13905 diff changeset	653 platform_type = HW_MICROSOFT;
0291cd939b43 3506 Use "hypervisor" CPUID bit to detect hypervisor environment Yuri Pankov <yuri.pankov@nexenta.com> parents: 13905 diff changeset	654 } else {
0291cd939b43 3506 Use "hypervisor" CPUID bit to detect hypervisor environment Yuri Pankov <yuri.pankov@nexenta.com> parents: 13905 diff changeset	655 /*
0291cd939b43 3506 Use "hypervisor" CPUID bit to detect hypervisor environment Yuri Pankov <yuri.pankov@nexenta.com> parents: 13905 diff changeset	656 * Check older VMware hardware versions. VMware hypervisor is
0291cd939b43 3506 Use "hypervisor" CPUID bit to detect hypervisor environment Yuri Pankov <yuri.pankov@nexenta.com> parents: 13905 diff changeset	657 * detected by performing an IN operation to VMware hypervisor
0291cd939b43 3506 Use "hypervisor" CPUID bit to detect hypervisor environment Yuri Pankov <yuri.pankov@nexenta.com> parents: 13905 diff changeset	658 * port and checking that value returned in %ebx is VMware
0291cd939b43 3506 Use "hypervisor" CPUID bit to detect hypervisor environment Yuri Pankov <yuri.pankov@nexenta.com> parents: 13905 diff changeset	659 * hypervisor magic value.
0291cd939b43 3506 Use "hypervisor" CPUID bit to detect hypervisor environment Yuri Pankov <yuri.pankov@nexenta.com> parents: 13905 diff changeset	660 *
0291cd939b43 3506 Use "hypervisor" CPUID bit to detect hypervisor environment Yuri Pankov <yuri.pankov@nexenta.com> parents: 13905 diff changeset	661 * References: http://kb.vmware.com/kb/1009458
0291cd939b43 3506 Use "hypervisor" CPUID bit to detect hypervisor environment Yuri Pankov <yuri.pankov@nexenta.com> parents: 13905 diff changeset	662 */
0291cd939b43 3506 Use "hypervisor" CPUID bit to detect hypervisor environment Yuri Pankov <yuri.pankov@nexenta.com> parents: 13905 diff changeset	663 vmware_port(VMWARE_HVCMD_GETVERSION, regs);
0291cd939b43 3506 Use "hypervisor" CPUID bit to detect hypervisor environment Yuri Pankov <yuri.pankov@nexenta.com> parents: 13905 diff changeset	664 if (regs[1] == VMWARE_HVMAGIC) {
0291cd939b43 3506 Use "hypervisor" CPUID bit to detect hypervisor environment Yuri Pankov <yuri.pankov@nexenta.com> parents: 13905 diff changeset	665 platform_type = HW_VMWARE;
0291cd939b43 3506 Use "hypervisor" CPUID bit to detect hypervisor environment Yuri Pankov <yuri.pankov@nexenta.com> parents: 13905 diff changeset	666 return;
0291cd939b43 3506 Use "hypervisor" CPUID bit to detect hypervisor environment Yuri Pankov <yuri.pankov@nexenta.com> parents: 13905 diff changeset	667 }
0291cd939b43 3506 Use "hypervisor" CPUID bit to detect hypervisor environment Yuri Pankov <yuri.pankov@nexenta.com> parents: 13905 diff changeset	668 }
0291cd939b43 3506 Use "hypervisor" CPUID bit to detect hypervisor environment Yuri Pankov <yuri.pankov@nexenta.com> parents: 13905 diff changeset	669
0291cd939b43 3506 Use "hypervisor" CPUID bit to detect hypervisor environment Yuri Pankov <yuri.pankov@nexenta.com> parents: 13905 diff changeset	670 /*
0291cd939b43 3506 Use "hypervisor" CPUID bit to detect hypervisor environment Yuri Pankov <yuri.pankov@nexenta.com> parents: 13905 diff changeset	671 * Check Xen hypervisor. In a fully virtualized domain,
0291cd939b43 3506 Use "hypervisor" CPUID bit to detect hypervisor environment Yuri Pankov <yuri.pankov@nexenta.com> parents: 13905 diff changeset	672 * Xen's pseudo-cpuid function returns a string representing the
0291cd939b43 3506 Use "hypervisor" CPUID bit to detect hypervisor environment Yuri Pankov <yuri.pankov@nexenta.com> parents: 13905 diff changeset	673 * Xen signature in %ebx, %ecx, and %edx. %eax contains the maximum
0291cd939b43 3506 Use "hypervisor" CPUID bit to detect hypervisor environment Yuri Pankov <yuri.pankov@nexenta.com> parents: 13905 diff changeset	674 * supported cpuid function. We need at least a (base + 2) leaf value
0291cd939b43 3506 Use "hypervisor" CPUID bit to detect hypervisor environment Yuri Pankov <yuri.pankov@nexenta.com> parents: 13905 diff changeset	675 * to do what we want to do. Try different base values, since the
0291cd939b43 3506 Use "hypervisor" CPUID bit to detect hypervisor environment Yuri Pankov <yuri.pankov@nexenta.com> parents: 13905 diff changeset	676 * hypervisor might use a different one depending on whether Hyper-V
0291cd939b43 3506 Use "hypervisor" CPUID bit to detect hypervisor environment Yuri Pankov <yuri.pankov@nexenta.com> parents: 13905 diff changeset	677 * emulation is switched on by default or not.
5741 58423876d513 PSARC 2007/664 Paravirtualized Drivers for Fully Virtualized xVM Domains mrj parents: 5438 diff changeset	678 */
12090 2986679fe0b5 6941777 determine_platform needs to do a better job inside a Xen HVM guest Frank Van Der Linden <Frank.Vanderlinden@Sun.COM> parents: 12004 diff changeset	679 for (base = 0x40000000; base < 0x40010000; base += 0x100) {
2986679fe0b5 6941777 determine_platform needs to do a better job inside a Xen HVM guest Frank Van Der Linden <Frank.Vanderlinden@Sun.COM> parents: 12004 diff changeset	680 cp.cp_eax = base;
2986679fe0b5 6941777 determine_platform needs to do a better job inside a Xen HVM guest Frank Van Der Linden <Frank.Vanderlinden@Sun.COM> parents: 12004 diff changeset	681 (void) __cpuid_insn(&cp);
14043 0291cd939b43 3506 Use "hypervisor" CPUID bit to detect hypervisor environment Yuri Pankov <yuri.pankov@nexenta.com> parents: 13905 diff changeset	682 regs[0] = cp.cp_ebx;
0291cd939b43 3506 Use "hypervisor" CPUID bit to detect hypervisor environment Yuri Pankov <yuri.pankov@nexenta.com> parents: 13905 diff changeset	683 regs[1] = cp.cp_ecx;
0291cd939b43 3506 Use "hypervisor" CPUID bit to detect hypervisor environment Yuri Pankov <yuri.pankov@nexenta.com> parents: 13905 diff changeset	684 regs[2] = cp.cp_edx;
0291cd939b43 3506 Use "hypervisor" CPUID bit to detect hypervisor environment Yuri Pankov <yuri.pankov@nexenta.com> parents: 13905 diff changeset	685 regs[3] = 0;
0291cd939b43 3506 Use "hypervisor" CPUID bit to detect hypervisor environment Yuri Pankov <yuri.pankov@nexenta.com> parents: 13905 diff changeset	686 if (strcmp(hvstr, HVSIG_XEN_HVM) == 0 &&
12090 2986679fe0b5 6941777 determine_platform needs to do a better job inside a Xen HVM guest Frank Van Der Linden <Frank.Vanderlinden@Sun.COM> parents: 12004 diff changeset	687 cp.cp_eax >= (base + 2)) {
14043 0291cd939b43 3506 Use "hypervisor" CPUID bit to detect hypervisor environment Yuri Pankov <yuri.pankov@nexenta.com> parents: 13905 diff changeset	688 platform_type &= ~HW_NATIVE;
0291cd939b43 3506 Use "hypervisor" CPUID bit to detect hypervisor environment Yuri Pankov <yuri.pankov@nexenta.com> parents: 13905 diff changeset	689 platform_type \|= HW_XEN_HVM;
12090 2986679fe0b5 6941777 determine_platform needs to do a better job inside a Xen HVM guest Frank Van Der Linden <Frank.Vanderlinden@Sun.COM> parents: 12004 diff changeset	690 return;
2986679fe0b5 6941777 determine_platform needs to do a better job inside a Xen HVM guest Frank Van Der Linden <Frank.Vanderlinden@Sun.COM> parents: 12004 diff changeset	691 }
2986679fe0b5 6941777 determine_platform needs to do a better job inside a Xen HVM guest Frank Van Der Linden <Frank.Vanderlinden@Sun.COM> parents: 12004 diff changeset	692 }
9000 7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	693 }
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	694
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	695 int
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	696 get_hwenv(void)
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	697 {
13498 e702644ca141 1687 Race in determine_platform / get_hwenv causes multi-CPU VM hang at boot Matt Amdur <mba@delphix.com> parents: 13425 diff changeset	698 ASSERT(platform_type != -1);
9000 7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	699 return (platform_type);
5741 58423876d513 PSARC 2007/664 Paravirtualized Drivers for Fully Virtualized xVM Domains mrj parents: 5438 diff changeset	700 }
9000 7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	701
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	702 int
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	703 is_controldom(void)
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	704 {
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	705 return (0);
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	706 }
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	707
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	708 #else
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	709
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	710 int
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	711 get_hwenv(void)
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	712 {
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	713 return (HW_XEN_PV);
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	714 }
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	715
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	716 int
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	717 is_controldom(void)
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	718 {
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	719 return (DOMAIN_IS_INITDOMAIN(xen_info));
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	720 }
7a9c5c9ed60d 6775011 bad trap page fault while starting dom0 Stuart Maybee <Stuart.Maybee@Sun.COM> parents: 8990 diff changeset	721
5741 58423876d513 PSARC 2007/664 Paravirtualized Drivers for Fully Virtualized xVM Domains mrj parents: 5438 diff changeset	722 #endif /* __xpv */
58423876d513 PSARC 2007/664 Paravirtualized Drivers for Fully Virtualized xVM Domains mrj parents: 5438 diff changeset	723
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	724 static void
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	725 cpuid_intel_getids(cpu_t cpu, void feature)
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	726 {
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	727 uint_t i;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	728 uint_t chipid_shift = 0;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	729 uint_t coreid_shift = 0;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	730 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	731
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	732 for (i = 1; i < cpi->cpi_ncpu_per_chip; i <<= 1)
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	733 chipid_shift++;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	734
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	735 cpi->cpi_chipid = cpi->cpi_apicid >> chipid_shift;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	736 cpi->cpi_clogid = cpi->cpi_apicid & ((1 << chipid_shift) - 1);
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	737
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	738 if (is_x86_feature(feature, X86FSET_CMP)) {
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	739 /*
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	740 * Multi-core (and possibly multi-threaded)
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	741 * processors.
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	742 */
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	743 uint_t ncpu_per_core;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	744 if (cpi->cpi_ncore_per_chip == 1)
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	745 ncpu_per_core = cpi->cpi_ncpu_per_chip;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	746 else if (cpi->cpi_ncore_per_chip > 1)
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	747 ncpu_per_core = cpi->cpi_ncpu_per_chip /
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	748 cpi->cpi_ncore_per_chip;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	749 /*
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	750 * 8bit APIC IDs on dual core Pentiums
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	751 * look like this:
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	752 *
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	753 * +-----------------------+------+------+
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	754 * \| Physical Package ID \| MC \| HT \|
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	755 * +-----------------------+------+------+
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	756 * <------- chipid -------->
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	757 * <------- coreid --------------->
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	758 * <--- clogid -->
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	759 * <------>
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	760 * pkgcoreid
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	761 *
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	762 * Where the number of bits necessary to
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	763 * represent MC and HT fields together equals
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	764 * to the minimum number of bits necessary to
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	765 * store the value of cpi->cpi_ncpu_per_chip.
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	766 * Of those bits, the MC part uses the number
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	767 * of bits necessary to store the value of
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	768 * cpi->cpi_ncore_per_chip.
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	769 */
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	770 for (i = 1; i < ncpu_per_core; i <<= 1)
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	771 coreid_shift++;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	772 cpi->cpi_coreid = cpi->cpi_apicid >> coreid_shift;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	773 cpi->cpi_pkgcoreid = cpi->cpi_clogid >> coreid_shift;
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	774 } else if (is_x86_feature(feature, X86FSET_HTT)) {
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	775 /*
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	776 * Single-core multi-threaded processors.
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	777 */
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	778 cpi->cpi_coreid = cpi->cpi_chipid;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	779 cpi->cpi_pkgcoreid = 0;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	780 }
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	781 cpi->cpi_procnodeid = cpi->cpi_chipid;
13681 73253247f9e5 2650 AMD family 0x15 PG support Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13675 diff changeset	782 cpi->cpi_compunitid = cpi->cpi_coreid;
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	783 }
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	784
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	785 static void
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	786 cpuid_amd_getids(cpu_t *cpu)
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	787 {
11013 3aa288b66f8e 6899212 cmi_hdl_impl structure is not exactly duplicated in the generic_cpu mdb module Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10992 diff changeset	788 int i, first_half, coreidsz;
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	789 uint32_t nb_caps_reg;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	790 uint_t node2_1;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	791 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
13681 73253247f9e5 2650 AMD family 0x15 PG support Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13675 diff changeset	792 struct cpuid_regs *cp;
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	793
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	794 /*
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	795 * AMD CMP chips currently have a single thread per core.
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	796 *
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	797 * Since no two cpus share a core we must assign a distinct coreid
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	798 * per cpu, and we do this by using the cpu_id. This scheme does not,
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	799 * however, guarantee that sibling cores of a chip will have sequential
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	800 * coreids starting at a multiple of the number of cores per chip -
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	801 * that is usually the case, but if the ACPI MADT table is presented
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	802 * in a different order then we need to perform a few more gymnastics
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	803 * for the pkgcoreid.
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	804 *
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	805 * All processors in the system have the same number of enabled
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	806 * cores. Cores within a processor are always numbered sequentially
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	807 * from 0 regardless of how many or which are disabled, and there
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	808 * is no way for operating system to discover the real core id when some
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	809 * are disabled.
13681 73253247f9e5 2650 AMD family 0x15 PG support Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13675 diff changeset	810 *
73253247f9e5 2650 AMD family 0x15 PG support Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13675 diff changeset	811 * In family 0x15, the cores come in pairs called compute units. They
73253247f9e5 2650 AMD family 0x15 PG support Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13675 diff changeset	812 * share I$ and L2 caches and the FPU. Enumeration of this feature is
73253247f9e5 2650 AMD family 0x15 PG support Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13675 diff changeset	813 * simplified by the new topology extensions CPUID leaf, indicated by
73253247f9e5 2650 AMD family 0x15 PG support Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13675 diff changeset	814 * the X86 feature X86FSET_TOPOEXT.
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	815 */
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	816
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	817 cpi->cpi_coreid = cpu->cpu_id;
13681 73253247f9e5 2650 AMD family 0x15 PG support Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13675 diff changeset	818 cpi->cpi_compunitid = cpu->cpu_id;
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	819
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	820 if (cpi->cpi_xmaxeax >= 0x80000008) {
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	821
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	822 coreidsz = BITX((cpi)->cpi_extd[8].cp_ecx, 15, 12);
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	823
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	824 /*
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	825 * In AMD parlance chip is really a node while Solaris
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	826 * sees chip as equivalent to socket/package.
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	827 */
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	828 cpi->cpi_ncore_per_chip =
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	829 BITX((cpi)->cpi_extd[8].cp_ecx, 7, 0) + 1;
11013 3aa288b66f8e 6899212 cmi_hdl_impl structure is not exactly duplicated in the generic_cpu mdb module Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10992 diff changeset	830 if (coreidsz == 0) {
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	831 /* Use legacy method */
11013 3aa288b66f8e 6899212 cmi_hdl_impl structure is not exactly duplicated in the generic_cpu mdb module Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10992 diff changeset	832 for (i = 1; i < cpi->cpi_ncore_per_chip; i <<= 1)
3aa288b66f8e 6899212 cmi_hdl_impl structure is not exactly duplicated in the generic_cpu mdb module Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10992 diff changeset	833 coreidsz++;
3aa288b66f8e 6899212 cmi_hdl_impl structure is not exactly duplicated in the generic_cpu mdb module Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10992 diff changeset	834 if (coreidsz == 0)
3aa288b66f8e 6899212 cmi_hdl_impl structure is not exactly duplicated in the generic_cpu mdb module Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10992 diff changeset	835 coreidsz = 1;
3aa288b66f8e 6899212 cmi_hdl_impl structure is not exactly duplicated in the generic_cpu mdb module Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10992 diff changeset	836 }
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	837 } else {
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	838 /* Assume single-core part */
11013 3aa288b66f8e 6899212 cmi_hdl_impl structure is not exactly duplicated in the generic_cpu mdb module Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10992 diff changeset	839 cpi->cpi_ncore_per_chip = 1;
12726 8f2fba7fcf9c 6957730 cpuid_amd_getids() uses uninitialized variable coreidsz Jakub Jermar <Jakub.Jermar@Sun.COM> parents: 12261 diff changeset	840 coreidsz = 1;
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	841 }
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	842
11013 3aa288b66f8e 6899212 cmi_hdl_impl structure is not exactly duplicated in the generic_cpu mdb module Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10992 diff changeset	843 cpi->cpi_clogid = cpi->cpi_pkgcoreid =
3aa288b66f8e 6899212 cmi_hdl_impl structure is not exactly duplicated in the generic_cpu mdb module Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10992 diff changeset	844 cpi->cpi_apicid & ((1<<coreidsz) - 1);
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	845 cpi->cpi_ncpu_per_chip = cpi->cpi_ncore_per_chip;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	846
13681 73253247f9e5 2650 AMD family 0x15 PG support Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13675 diff changeset	847 /* Get node ID, compute unit ID */
73253247f9e5 2650 AMD family 0x15 PG support Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13675 diff changeset	848 if (is_x86_feature(x86_featureset, X86FSET_TOPOEXT) &&
73253247f9e5 2650 AMD family 0x15 PG support Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13675 diff changeset	849 cpi->cpi_xmaxeax >= 0x8000001e) {
73253247f9e5 2650 AMD family 0x15 PG support Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13675 diff changeset	850 cp = &cpi->cpi_extd[0x1e];
73253247f9e5 2650 AMD family 0x15 PG support Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13675 diff changeset	851 cp->cp_eax = 0x8000001e;
73253247f9e5 2650 AMD family 0x15 PG support Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13675 diff changeset	852 (void) __cpuid_insn(cp);
73253247f9e5 2650 AMD family 0x15 PG support Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13675 diff changeset	853
73253247f9e5 2650 AMD family 0x15 PG support Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13675 diff changeset	854 cpi->cpi_procnodes_per_pkg = BITX(cp->cp_ecx, 10, 8) + 1;
73253247f9e5 2650 AMD family 0x15 PG support Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13675 diff changeset	855 cpi->cpi_procnodeid = BITX(cp->cp_ecx, 7, 0);
73253247f9e5 2650 AMD family 0x15 PG support Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13675 diff changeset	856 cpi->cpi_cores_per_compunit = BITX(cp->cp_ebx, 15, 8) + 1;
73253247f9e5 2650 AMD family 0x15 PG support Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13675 diff changeset	857 cpi->cpi_compunitid = BITX(cp->cp_ebx, 7, 0)
73253247f9e5 2650 AMD family 0x15 PG support Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13675 diff changeset	858 + (cpi->cpi_ncore_per_chip / cpi->cpi_cores_per_compunit)
73253247f9e5 2650 AMD family 0x15 PG support Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13675 diff changeset	859 * (cpi->cpi_procnodeid / cpi->cpi_procnodes_per_pkg);
73253247f9e5 2650 AMD family 0x15 PG support Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13675 diff changeset	860 } else if (cpi->cpi_family == 0xf \|\| cpi->cpi_family >= 0x11) {
11013 3aa288b66f8e 6899212 cmi_hdl_impl structure is not exactly duplicated in the generic_cpu mdb module Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10992 diff changeset	861 cpi->cpi_procnodeid = (cpi->cpi_apicid >> coreidsz) & 7;
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	862 } else if (cpi->cpi_family == 0x10) {
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	863 /*
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	864 * See if we are a multi-node processor.
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	865 * All processors in the system have the same number of nodes
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	866 */
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	867 nb_caps_reg = pci_getl_func(0, 24, 3, 0xe8);
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	868 if ((cpi->cpi_model < 8) \|\| BITX(nb_caps_reg, 29, 29) == 0) {
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	869 /* Single-node */
11013 3aa288b66f8e 6899212 cmi_hdl_impl structure is not exactly duplicated in the generic_cpu mdb module Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10992 diff changeset	870 cpi->cpi_procnodeid = BITX(cpi->cpi_apicid, 5,
3aa288b66f8e 6899212 cmi_hdl_impl structure is not exactly duplicated in the generic_cpu mdb module Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10992 diff changeset	871 coreidsz);
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	872 } else {
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	873
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	874 /*
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	875 * Multi-node revision D (2 nodes per package
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	876 * are supported)
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	877 */
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	878 cpi->cpi_procnodes_per_pkg = 2;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	879
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	880 first_half = (cpi->cpi_pkgcoreid <=
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	881 (cpi->cpi_ncore_per_chip/2 - 1));
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	882
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	883 if (cpi->cpi_apicid == cpi->cpi_pkgcoreid) {
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	884 /* We are BSP */
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	885 cpi->cpi_procnodeid = (first_half ? 0 : 1);
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	886 } else {
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	887
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	888 /* We are AP */
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	889 /* NodeId[2:1] bits to use for reading F3xe8 */
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	890 node2_1 = BITX(cpi->cpi_apicid, 5, 4) << 1;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	891
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	892 nb_caps_reg =
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	893 pci_getl_func(0, 24 + node2_1, 3, 0xe8);
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	894
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	895 /*
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	896 * Check IntNodeNum bit (31:30, but bit 31 is
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	897 * always 0 on dual-node processors)
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	898 */
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	899 if (BITX(nb_caps_reg, 30, 30) == 0)
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	900 cpi->cpi_procnodeid = node2_1 +
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	901 !first_half;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	902 else
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	903 cpi->cpi_procnodeid = node2_1 +
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	904 first_half;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	905 }
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	906 }
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	907 } else {
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	908 cpi->cpi_procnodeid = 0;
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	909 }
13681 73253247f9e5 2650 AMD family 0x15 PG support Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13675 diff changeset	910
73253247f9e5 2650 AMD family 0x15 PG support Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13675 diff changeset	911 cpi->cpi_chipid =
73253247f9e5 2650 AMD family 0x15 PG support Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13675 diff changeset	912 cpi->cpi_procnodeid / cpi->cpi_procnodes_per_pkg;
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	913 }
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	914
13146 8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	915 /*
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	916 * Setup XFeature_Enabled_Mask register. Required by xsave feature.
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	917 */
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	918 void
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	919 setup_xfem(void)
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	920 {
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	921 uint64_t flags = XFEATURE_LEGACY_FP;
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	922
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	923 ASSERT(is_x86_feature(x86_featureset, X86FSET_XSAVE));
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	924
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	925 if (is_x86_feature(x86_featureset, X86FSET_SSE))
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	926 flags \|= XFEATURE_SSE;
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	927
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	928 if (is_x86_feature(x86_featureset, X86FSET_AVX))
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	929 flags \|= XFEATURE_AVX;
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	930
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	931 set_xcr(XFEATURE_ENABLED_MASK, flags);
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	932
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	933 xsave_bv_all = flags;
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	934 }
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	935
13148 67d1861e02c1 6970888 panic BAD TRAP: type=d (#gp General protection) due to incorrect use of x86_featureset Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13146 diff changeset	936 void
67d1861e02c1 6970888 panic BAD TRAP: type=d (#gp General protection) due to incorrect use of x86_featureset Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13146 diff changeset	937 cpuid_pass1(cpu_t cpu, uchar_t featureset)
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	938 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	939 uint32_t mask_ecx, mask_edx;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	940 struct cpuid_info *cpi;
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	941 struct cpuid_regs *cp;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	942 int xcpuid;
5084 7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	943 #if !defined(__xpv)
5045 75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	944 extern int idle_cpu_prefer_mwait;
5084 7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	945 #endif
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	946
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	947 /*
12004 93f274d4a367 PSARC/2009/104 Hot-Plug Support for ACPI-based Systems Gerry Liu <jiang.liu@intel.com> parents: 11919 diff changeset	948 * Space statically allocated for BSP, ensure pointer is set
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	949 */
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	950 if (cpu->cpu_id == 0) {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	951 if (cpu->cpu_m.mcpu_cpi == NULL)
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	952 cpu->cpu_m.mcpu_cpi = &cpuid_info0;
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	953 }
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	954
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	955 add_x86_feature(featureset, X86FSET_CPUID);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	956
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	957 cpi = cpu->cpu_m.mcpu_cpi;
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	958 ASSERT(cpi != NULL);
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	959 cp = &cpi->cpi_std[0];
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	960 cp->cp_eax = 0;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	961 cpi->cpi_maxeax = __cpuid_insn(cp);
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	962 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	963 uint32_t iptr = (uint32_t )cpi->cpi_vendorstr;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	964 *iptr++ = cp->cp_ebx;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	965 *iptr++ = cp->cp_edx;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	966 *iptr++ = cp->cp_ecx;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	967 (char )&cpi->cpi_vendorstr[12] = '\0';
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	968 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	969
7532 bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	970 cpi->cpi_vendor = _cpuid_vendorstr_to_vendorcode(cpi->cpi_vendorstr);
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	971 x86_vendor = cpi->cpi_vendor; /* for compatibility */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	972
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	973 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	974 * Limit the range in case of weird hardware
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	975 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	976 if (cpi->cpi_maxeax > CPI_MAXEAX_MAX)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	977 cpi->cpi_maxeax = CPI_MAXEAX_MAX;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	978 if (cpi->cpi_maxeax < 1)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	979 goto pass1_done;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	980
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	981 cp = &cpi->cpi_std[1];
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	982 cp->cp_eax = 1;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	983 (void) __cpuid_insn(cp);
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	984
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	985 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	986 * Extract identifying constants for easy access.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	987 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	988 cpi->cpi_model = CPI_MODEL(cpi);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	989 cpi->cpi_family = CPI_FAMILY(cpi);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	990
1975 7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	991 if (cpi->cpi_family == 0xf)
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	992 cpi->cpi_family += CPI_FAMILY_XTD(cpi);
1975 7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	993
2001 427a702b03e2 6427092 extended-model CPUID information is different between AMD and Intel dmick parents: 1975 diff changeset	994 /*
4265 6be078c4d3b4 6555108 workarounds being applied for errata not present in greyhound processors kchow parents: 3779 diff changeset	995 * Beware: AMD uses "extended model" iff base FAMILY == 0xf.
2001 427a702b03e2 6427092 extended-model CPUID information is different between AMD and Intel dmick parents: 1975 diff changeset	996 * Intel, and presumably everyone else, uses model == 0xf, as
427a702b03e2 6427092 extended-model CPUID information is different between AMD and Intel dmick parents: 1975 diff changeset	997 * one would expect (max value means possible overflow). Sigh.
427a702b03e2 6427092 extended-model CPUID information is different between AMD and Intel dmick parents: 1975 diff changeset	998 */
427a702b03e2 6427092 extended-model CPUID information is different between AMD and Intel dmick parents: 1975 diff changeset	999
427a702b03e2 6427092 extended-model CPUID information is different between AMD and Intel dmick parents: 1975 diff changeset	1000 switch (cpi->cpi_vendor) {
4855 3319ad80f260 6574102 Need to add extended family/model/stepping info to cpuid_pass1() for Intel processors ksadhukh parents: 4797 diff changeset	1001 case X86_VENDOR_Intel:
3319ad80f260 6574102 Need to add extended family/model/stepping info to cpuid_pass1() for Intel processors ksadhukh parents: 4797 diff changeset	1002 if (IS_EXTENDED_MODEL_INTEL(cpi))
3319ad80f260 6574102 Need to add extended family/model/stepping info to cpuid_pass1() for Intel processors ksadhukh parents: 4797 diff changeset	1003 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4;
4858 08409e2eed12 6574102 Need to add extended family/model/stepping info to cpuid_pass1() for Intel processors (fix lint) ksadhukh parents: 4855 diff changeset	1004 break;
2001 427a702b03e2 6427092 extended-model CPUID information is different between AMD and Intel dmick parents: 1975 diff changeset	1005 case X86_VENDOR_AMD:
4265 6be078c4d3b4 6555108 workarounds being applied for errata not present in greyhound processors kchow parents: 3779 diff changeset	1006 if (CPI_FAMILY(cpi) == 0xf)
2001 427a702b03e2 6427092 extended-model CPUID information is different between AMD and Intel dmick parents: 1975 diff changeset	1007 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4;
427a702b03e2 6427092 extended-model CPUID information is different between AMD and Intel dmick parents: 1975 diff changeset	1008 break;
427a702b03e2 6427092 extended-model CPUID information is different between AMD and Intel dmick parents: 1975 diff changeset	1009 default:
427a702b03e2 6427092 extended-model CPUID information is different between AMD and Intel dmick parents: 1975 diff changeset	1010 if (cpi->cpi_model == 0xf)
427a702b03e2 6427092 extended-model CPUID information is different between AMD and Intel dmick parents: 1975 diff changeset	1011 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4;
427a702b03e2 6427092 extended-model CPUID information is different between AMD and Intel dmick parents: 1975 diff changeset	1012 break;
427a702b03e2 6427092 extended-model CPUID information is different between AMD and Intel dmick parents: 1975 diff changeset	1013 }
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1014
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1015 cpi->cpi_step = CPI_STEP(cpi);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1016 cpi->cpi_brandid = CPI_BRANDID(cpi);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1017
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1018 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1019 * default assumptions:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1020 * - believe %edx feature word
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1021 * - ignore %ecx feature word
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1022 * - 32-bit virtual and physical addressing
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1023 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1024 mask_edx = 0xffffffff;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1025 mask_ecx = 0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1026
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1027 cpi->cpi_pabits = cpi->cpi_vabits = 32;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1028
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1029 switch (cpi->cpi_vendor) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1030 case X86_VENDOR_Intel:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1031 if (cpi->cpi_family == 5)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1032 x86_type = X86_TYPE_P5;
1975 7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	1033 else if (IS_LEGACY_P6(cpi)) {
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1034 x86_type = X86_TYPE_P6;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1035 pentiumpro_bug4046376 = 1;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1036 pentiumpro_bug4064495 = 1;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1037 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1038 * Clear the SEP bit when it was set erroneously
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1039 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1040 if (cpi->cpi_model < 3 && cpi->cpi_step < 3)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1041 cp->cp_edx &= ~CPUID_INTC_EDX_SEP;
1975 7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	1042 } else if (IS_NEW_F6(cpi) \|\| cpi->cpi_family == 0xf) {
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1043 x86_type = X86_TYPE_P4;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1044 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1045 * We don't currently depend on any of the %ecx
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1046 * features until Prescott, so we'll only check
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1047 * this from P4 onwards. We might want to revisit
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1048 * that idea later.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1049 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1050 mask_ecx = 0xffffffff;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1051 } else if (cpi->cpi_family > 0xf)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1052 mask_ecx = 0xffffffff;
4636 f7779128d972 6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0 bholler parents: 4628 diff changeset	1053 /*
f7779128d972 6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0 bholler parents: 4628 diff changeset	1054 * We don't support MONITOR/MWAIT if leaf 5 is not available
f7779128d972 6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0 bholler parents: 4628 diff changeset	1055 * to obtain the monitor linesize.
f7779128d972 6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0 bholler parents: 4628 diff changeset	1056 */
f7779128d972 6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0 bholler parents: 4628 diff changeset	1057 if (cpi->cpi_maxeax < 5)
f7779128d972 6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0 bholler parents: 4628 diff changeset	1058 mask_ecx &= ~CPUID_INTC_ECX_MON;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1059 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1060 case X86_VENDOR_IntelClone:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1061 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1062 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1063 case X86_VENDOR_AMD:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1064 #if defined(OPTERON_ERRATUM_108)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1065 if (cpi->cpi_family == 0xf && cpi->cpi_model == 0xe) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1066 cp->cp_eax = (0xf0f & cp->cp_eax) \| 0xc0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1067 cpi->cpi_model = 0xc;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1068 } else
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1069 #endif
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1070 if (cpi->cpi_family == 5) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1071 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1072 * AMD K5 and K6
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1073 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1074 * These CPUs have an incomplete implementation
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1075 * of MCA/MCE which we mask away.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1076 */
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1077 mask_edx &= ~(CPUID_INTC_EDX_MCE \| CPUID_INTC_EDX_MCA);
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1078
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1079 /*
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1080 * Model 0 uses the wrong (APIC) bit
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1081 * to indicate PGE. Fix it here.
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1082 */
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1083 if (cpi->cpi_model == 0) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1084 if (cp->cp_edx & 0x200) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1085 cp->cp_edx &= ~0x200;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1086 cp->cp_edx \|= CPUID_INTC_EDX_PGE;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1087 }
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1088 }
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1089
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1090 /*
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1091 * Early models had problems w/ MMX; disable.
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1092 */
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1093 if (cpi->cpi_model < 6)
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1094 mask_edx &= ~CPUID_INTC_EDX_MMX;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1095 }
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1096
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1097 /*
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1098 * For newer families, SSE3 and CX16, at least, are valid;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1099 * enable all
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1100 */
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1101 if (cpi->cpi_family >= 0xf)
771 1c25a2120ec0 6327969 cpuid sse3 feature bit not noted on any AMD processor dmick parents: 359 diff changeset	1102 mask_ecx = 0xffffffff;
4636 f7779128d972 6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0 bholler parents: 4628 diff changeset	1103 /*
f7779128d972 6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0 bholler parents: 4628 diff changeset	1104 * We don't support MONITOR/MWAIT if leaf 5 is not available
f7779128d972 6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0 bholler parents: 4628 diff changeset	1105 * to obtain the monitor linesize.
f7779128d972 6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0 bholler parents: 4628 diff changeset	1106 */
f7779128d972 6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0 bholler parents: 4628 diff changeset	1107 if (cpi->cpi_maxeax < 5)
f7779128d972 6577473 Nocona box panic when booting snv_68: Can't handle mwait size 0 bholler parents: 4628 diff changeset	1108 mask_ecx &= ~CPUID_INTC_ECX_MON;
5045 75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1109
5084 7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	1110 #if !defined(__xpv)
5045 75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1111 /*
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1112 * Do not use MONITOR/MWAIT to halt in the idle loop on any AMD
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1113 * processors. AMD does not intend MWAIT to be used in the cpu
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1114 * idle loop on current and future processors. 10h and future
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1115 * AMD processors use more power in MWAIT than HLT.
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1116 * Pre-family-10h Opterons do not have the MWAIT instruction.
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1117 */
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1118 idle_cpu_prefer_mwait = 0;
5084 7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	1119 #endif
5045 75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1120
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1121 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1122 case X86_VENDOR_TM:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1123 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1124 * workaround the NT workaround in CMS 4.1
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1125 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1126 if (cpi->cpi_family == 5 && cpi->cpi_model == 4 &&
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1127 (cpi->cpi_step == 2 \|\| cpi->cpi_step == 3))
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1128 cp->cp_edx \|= CPUID_INTC_EDX_CX8;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1129 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1130 case X86_VENDOR_Centaur:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1131 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1132 * workaround the NT workarounds again
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1133 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1134 if (cpi->cpi_family == 6)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1135 cp->cp_edx \|= CPUID_INTC_EDX_CX8;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1136 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1137 case X86_VENDOR_Cyrix:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1138 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1139 * We rely heavily on the probing in locore
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1140 * to actually figure out what parts, if any,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1141 * of the Cyrix cpuid instruction to believe.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1142 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1143 switch (x86_type) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1144 case X86_TYPE_CYRIX_486:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1145 mask_edx = 0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1146 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1147 case X86_TYPE_CYRIX_6x86:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1148 mask_edx = 0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1149 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1150 case X86_TYPE_CYRIX_6x86L:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1151 mask_edx =
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1152 CPUID_INTC_EDX_DE \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1153 CPUID_INTC_EDX_CX8;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1154 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1155 case X86_TYPE_CYRIX_6x86MX:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1156 mask_edx =
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1157 CPUID_INTC_EDX_DE \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1158 CPUID_INTC_EDX_MSR \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1159 CPUID_INTC_EDX_CX8 \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1160 CPUID_INTC_EDX_PGE \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1161 CPUID_INTC_EDX_CMOV \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1162 CPUID_INTC_EDX_MMX;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1163 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1164 case X86_TYPE_CYRIX_GXm:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1165 mask_edx =
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1166 CPUID_INTC_EDX_MSR \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1167 CPUID_INTC_EDX_CX8 \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1168 CPUID_INTC_EDX_CMOV \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1169 CPUID_INTC_EDX_MMX;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1170 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1171 case X86_TYPE_CYRIX_MediaGX:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1172 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1173 case X86_TYPE_CYRIX_MII:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1174 case X86_TYPE_VIA_CYRIX_III:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1175 mask_edx =
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1176 CPUID_INTC_EDX_DE \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1177 CPUID_INTC_EDX_TSC \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1178 CPUID_INTC_EDX_MSR \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1179 CPUID_INTC_EDX_CX8 \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1180 CPUID_INTC_EDX_PGE \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1181 CPUID_INTC_EDX_CMOV \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1182 CPUID_INTC_EDX_MMX;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1183 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1184 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1185 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1186 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1187 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1188 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1189
5084 7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	1190 #if defined(__xpv)
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	1191 /*
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	1192 * Do not support MONITOR/MWAIT under a hypervisor
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	1193 */
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	1194 mask_ecx &= ~CPUID_INTC_ECX_MON;
13146 8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1195 /*
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1196 * Do not support XSAVE under a hypervisor for now
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1197 */
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1198 xsave_force_disable = B_TRUE;
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1199
5084 7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	1200 #endif /* __xpv */
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	1201
13146 8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1202 if (xsave_force_disable) {
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1203 mask_ecx &= ~CPUID_INTC_ECX_XSAVE;
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1204 mask_ecx &= ~CPUID_INTC_ECX_AVX;
13905 b151bd260b71 3414 Need a new word of AT_SUN_HWCAP bits Robert Mustacchi <rm@joyent.com> parents: 13681 diff changeset	1205 mask_ecx &= ~CPUID_INTC_ECX_F16C;
13146 8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1206 }
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1207
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1208 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1209 * Now we've figured out the masks that determine
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1210 * which bits we choose to believe, apply the masks
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1211 * to the feature words, then map the kernel's view
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1212 * of these feature words into its feature word.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1213 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1214 cp->cp_edx &= mask_edx;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1215 cp->cp_ecx &= mask_ecx;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1216
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1217 /*
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	1218 * apply any platform restrictions (we don't call this
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	1219 * immediately after __cpuid_insn here, because we need the
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	1220 * workarounds applied above first)
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1221 */
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	1222 platform_cpuid_mangle(cpi->cpi_vendor, 1, cp);
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1223
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	1224 /*
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	1225 * fold in overrides from the "eeprom" mechanism
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	1226 */
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1227 cp->cp_edx \|= cpuid_feature_edx_include;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1228 cp->cp_edx &= ~cpuid_feature_edx_exclude;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1229
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1230 cp->cp_ecx \|= cpuid_feature_ecx_include;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1231 cp->cp_ecx &= ~cpuid_feature_ecx_exclude;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1232
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1233 if (cp->cp_edx & CPUID_INTC_EDX_PSE) {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1234 add_x86_feature(featureset, X86FSET_LARGEPAGE);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1235 }
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1236 if (cp->cp_edx & CPUID_INTC_EDX_TSC) {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1237 add_x86_feature(featureset, X86FSET_TSC);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1238 }
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1239 if (cp->cp_edx & CPUID_INTC_EDX_MSR) {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1240 add_x86_feature(featureset, X86FSET_MSR);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1241 }
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1242 if (cp->cp_edx & CPUID_INTC_EDX_MTRR) {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1243 add_x86_feature(featureset, X86FSET_MTRR);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1244 }
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1245 if (cp->cp_edx & CPUID_INTC_EDX_PGE) {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1246 add_x86_feature(featureset, X86FSET_PGE);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1247 }
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1248 if (cp->cp_edx & CPUID_INTC_EDX_CMOV) {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1249 add_x86_feature(featureset, X86FSET_CMOV);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1250 }
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1251 if (cp->cp_edx & CPUID_INTC_EDX_MMX) {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1252 add_x86_feature(featureset, X86FSET_MMX);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1253 }
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1254 if ((cp->cp_edx & CPUID_INTC_EDX_MCE) != 0 &&
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1255 (cp->cp_edx & CPUID_INTC_EDX_MCA) != 0) {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1256 add_x86_feature(featureset, X86FSET_MCA);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1257 }
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1258 if (cp->cp_edx & CPUID_INTC_EDX_PAE) {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1259 add_x86_feature(featureset, X86FSET_PAE);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1260 }
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1261 if (cp->cp_edx & CPUID_INTC_EDX_CX8) {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1262 add_x86_feature(featureset, X86FSET_CX8);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1263 }
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1264 if (cp->cp_ecx & CPUID_INTC_ECX_CX16) {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1265 add_x86_feature(featureset, X86FSET_CX16);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1266 }
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1267 if (cp->cp_edx & CPUID_INTC_EDX_PAT) {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1268 add_x86_feature(featureset, X86FSET_PAT);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1269 }
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1270 if (cp->cp_edx & CPUID_INTC_EDX_SEP) {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1271 add_x86_feature(featureset, X86FSET_SEP);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1272 }
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1273 if (cp->cp_edx & CPUID_INTC_EDX_FXSR) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1274 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1275 * In our implementation, fxsave/fxrstor
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1276 * are prerequisites before we'll even
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1277 * try and do SSE things.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1278 */
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1279 if (cp->cp_edx & CPUID_INTC_EDX_SSE) {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1280 add_x86_feature(featureset, X86FSET_SSE);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1281 }
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1282 if (cp->cp_edx & CPUID_INTC_EDX_SSE2) {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1283 add_x86_feature(featureset, X86FSET_SSE2);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1284 }
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1285 if (cp->cp_ecx & CPUID_INTC_ECX_SSE3) {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1286 add_x86_feature(featureset, X86FSET_SSE3);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1287 }
13655 0461a7e94e53 2412 Various CPU features aren't intel specific Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13651 diff changeset	1288 if (cp->cp_ecx & CPUID_INTC_ECX_SSSE3) {
0461a7e94e53 2412 Various CPU features aren't intel specific Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13651 diff changeset	1289 add_x86_feature(featureset, X86FSET_SSSE3);
0461a7e94e53 2412 Various CPU features aren't intel specific Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13651 diff changeset	1290 }
0461a7e94e53 2412 Various CPU features aren't intel specific Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13651 diff changeset	1291 if (cp->cp_ecx & CPUID_INTC_ECX_SSE4_1) {
0461a7e94e53 2412 Various CPU features aren't intel specific Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13651 diff changeset	1292 add_x86_feature(featureset, X86FSET_SSE4_1);
0461a7e94e53 2412 Various CPU features aren't intel specific Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13651 diff changeset	1293 }
0461a7e94e53 2412 Various CPU features aren't intel specific Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13651 diff changeset	1294 if (cp->cp_ecx & CPUID_INTC_ECX_SSE4_2) {
0461a7e94e53 2412 Various CPU features aren't intel specific Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13651 diff changeset	1295 add_x86_feature(featureset, X86FSET_SSE4_2);
0461a7e94e53 2412 Various CPU features aren't intel specific Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13651 diff changeset	1296 }
0461a7e94e53 2412 Various CPU features aren't intel specific Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13651 diff changeset	1297 if (cp->cp_ecx & CPUID_INTC_ECX_AES) {
0461a7e94e53 2412 Various CPU features aren't intel specific Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13651 diff changeset	1298 add_x86_feature(featureset, X86FSET_AES);
0461a7e94e53 2412 Various CPU features aren't intel specific Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13651 diff changeset	1299 }
0461a7e94e53 2412 Various CPU features aren't intel specific Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13651 diff changeset	1300 if (cp->cp_ecx & CPUID_INTC_ECX_PCLMULQDQ) {
0461a7e94e53 2412 Various CPU features aren't intel specific Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13651 diff changeset	1301 add_x86_feature(featureset, X86FSET_PCLMULQDQ);
0461a7e94e53 2412 Various CPU features aren't intel specific Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13651 diff changeset	1302 }
0461a7e94e53 2412 Various CPU features aren't intel specific Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13651 diff changeset	1303
0461a7e94e53 2412 Various CPU features aren't intel specific Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13651 diff changeset	1304 if (cp->cp_ecx & CPUID_INTC_ECX_XSAVE) {
0461a7e94e53 2412 Various CPU features aren't intel specific Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13651 diff changeset	1305 add_x86_feature(featureset, X86FSET_XSAVE);
13905 b151bd260b71 3414 Need a new word of AT_SUN_HWCAP bits Robert Mustacchi <rm@joyent.com> parents: 13681 diff changeset	1306
13655 0461a7e94e53 2412 Various CPU features aren't intel specific Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13651 diff changeset	1307 /* We only test AVX when there is XSAVE */
0461a7e94e53 2412 Various CPU features aren't intel specific Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13651 diff changeset	1308 if (cp->cp_ecx & CPUID_INTC_ECX_AVX) {
0461a7e94e53 2412 Various CPU features aren't intel specific Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13651 diff changeset	1309 add_x86_feature(featureset,
0461a7e94e53 2412 Various CPU features aren't intel specific Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13651 diff changeset	1310 X86FSET_AVX);
13905 b151bd260b71 3414 Need a new word of AT_SUN_HWCAP bits Robert Mustacchi <rm@joyent.com> parents: 13681 diff changeset	1311
b151bd260b71 3414 Need a new word of AT_SUN_HWCAP bits Robert Mustacchi <rm@joyent.com> parents: 13681 diff changeset	1312 if (cp->cp_ecx & CPUID_INTC_ECX_F16C)
b151bd260b71 3414 Need a new word of AT_SUN_HWCAP bits Robert Mustacchi <rm@joyent.com> parents: 13681 diff changeset	1313 add_x86_feature(featureset,
b151bd260b71 3414 Need a new word of AT_SUN_HWCAP bits Robert Mustacchi <rm@joyent.com> parents: 13681 diff changeset	1314 X86FSET_F16C);
13146 8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1315 }
5269 395a95dbfd17 6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors kk208521 parents: 5254 diff changeset	1316 }
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1317 }
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1318 if (cp->cp_edx & CPUID_INTC_EDX_DE) {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1319 add_x86_feature(featureset, X86FSET_DE);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1320 }
7716 44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1321 #if !defined(__xpv)
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1322 if (cp->cp_ecx & CPUID_INTC_ECX_MON) {
7716 44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1323
44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1324 /*
44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1325 * We require the CLFLUSH instruction for erratum workaround
44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1326 * to use MONITOR/MWAIT.
44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1327 */
44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1328 if (cp->cp_edx & CPUID_INTC_EDX_CLFSH) {
44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1329 cpi->cpi_mwait.support \|= MWAIT_SUPPORT;
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1330 add_x86_feature(featureset, X86FSET_MWAIT);
7716 44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1331 } else {
44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1332 extern int idle_cpu_assert_cflush_monitor;
44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1333
44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1334 /*
44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1335 * All processors we are aware of which have
44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1336 * MONITOR/MWAIT also have CLFLUSH.
44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1337 */
44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1338 if (idle_cpu_assert_cflush_monitor) {
44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1339 ASSERT((cp->cp_ecx & CPUID_INTC_ECX_MON) &&
44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1340 (cp->cp_edx & CPUID_INTC_EDX_CLFSH));
44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1341 }
44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1342 }
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1343 }
7716 44c2ec1382be 6726459 dunnington based tucani system has huge memory latency, almost 5x of tigerton based tucani system Bill Holler <Bill.Holler@Sun.COM> parents: 7656 diff changeset	1344 #endif /* __xpv */
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1345
13425 8640246a3548 1347 isainfo should indicate presence of vmx/svm support Bryan Cantrill <bryan@joyent.com> parents: 13148 diff changeset	1346 if (cp->cp_ecx & CPUID_INTC_ECX_VMX) {
8640246a3548 1347 isainfo should indicate presence of vmx/svm support Bryan Cantrill <bryan@joyent.com> parents: 13148 diff changeset	1347 add_x86_feature(featureset, X86FSET_VMX);
8640246a3548 1347 isainfo should indicate presence of vmx/svm support Bryan Cantrill <bryan@joyent.com> parents: 13148 diff changeset	1348 }
8640246a3548 1347 isainfo should indicate presence of vmx/svm support Bryan Cantrill <bryan@joyent.com> parents: 13148 diff changeset	1349
13905 b151bd260b71 3414 Need a new word of AT_SUN_HWCAP bits Robert Mustacchi <rm@joyent.com> parents: 13681 diff changeset	1350 if (cp->cp_ecx & CPUID_INTC_ECX_RDRAND)
b151bd260b71 3414 Need a new word of AT_SUN_HWCAP bits Robert Mustacchi <rm@joyent.com> parents: 13681 diff changeset	1351 add_x86_feature(featureset, X86FSET_RDRAND);
b151bd260b71 3414 Need a new word of AT_SUN_HWCAP bits Robert Mustacchi <rm@joyent.com> parents: 13681 diff changeset	1352
7589 7de800909a06 PSARC 2008/560 Intel IOMMU Vikram Hegde <Vikram.Hegde@Sun.COM> parents: 7532 diff changeset	1353 /*
13425 8640246a3548 1347 isainfo should indicate presence of vmx/svm support Bryan Cantrill <bryan@joyent.com> parents: 13148 diff changeset	1354 * Only need it first time, rest of the cpus would follow suit.
7589 7de800909a06 PSARC 2008/560 Intel IOMMU Vikram Hegde <Vikram.Hegde@Sun.COM> parents: 7532 diff changeset	1355 * we only capture this for the bootcpu.
7de800909a06 PSARC 2008/560 Intel IOMMU Vikram Hegde <Vikram.Hegde@Sun.COM> parents: 7532 diff changeset	1356 */
7de800909a06 PSARC 2008/560 Intel IOMMU Vikram Hegde <Vikram.Hegde@Sun.COM> parents: 7532 diff changeset	1357 if (cp->cp_edx & CPUID_INTC_EDX_CLFSH) {
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1358 add_x86_feature(featureset, X86FSET_CLFSH);
7589 7de800909a06 PSARC 2008/560 Intel IOMMU Vikram Hegde <Vikram.Hegde@Sun.COM> parents: 7532 diff changeset	1359 x86_clflush_size = (BITX(cp->cp_ebx, 15, 8) * 8);
7de800909a06 PSARC 2008/560 Intel IOMMU Vikram Hegde <Vikram.Hegde@Sun.COM> parents: 7532 diff changeset	1360 }
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1361 if (is_x86_feature(featureset, X86FSET_PAE))
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1362 cpi->cpi_pabits = 36;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1363
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1364 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1365 * Hyperthreading configuration is slightly tricky on Intel
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1366 * and pure clones, and even trickier on AMD.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1367 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1368 * (AMD chose to set the HTT bit on their CMP processors,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1369 * even though they're not actually hyperthreaded. Thus it
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1370 * takes a bit more work to figure out what's really going
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	1371 * on ... see the handling of the CMP_LGCY bit below)
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1372 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1373 if (cp->cp_edx & CPUID_INTC_EDX_HTT) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1374 cpi->cpi_ncpu_per_chip = CPI_CPU_COUNT(cpi);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1375 if (cpi->cpi_ncpu_per_chip > 1)
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1376 add_x86_feature(featureset, X86FSET_HTT);
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1377 } else {
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1378 cpi->cpi_ncpu_per_chip = 1;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1379 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1380
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1381 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1382 * Work on the "extended" feature information, doing
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1383 * some basic initialization for cpuid_pass2()
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1384 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1385 xcpuid = 0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1386 switch (cpi->cpi_vendor) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1387 case X86_VENDOR_Intel:
1975 7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	1388 if (IS_NEW_F6(cpi) \|\| cpi->cpi_family >= 0xf)
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1389 xcpuid++;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1390 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1391 case X86_VENDOR_AMD:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1392 if (cpi->cpi_family > 5 \|\|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1393 (cpi->cpi_family == 5 && cpi->cpi_model >= 1))
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1394 xcpuid++;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1395 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1396 case X86_VENDOR_Cyrix:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1397 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1398 * Only these Cyrix CPUs are -known- to support
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1399 * extended cpuid operations.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1400 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1401 if (x86_type == X86_TYPE_VIA_CYRIX_III \|\|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1402 x86_type == X86_TYPE_CYRIX_GXm)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1403 xcpuid++;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1404 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1405 case X86_VENDOR_Centaur:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1406 case X86_VENDOR_TM:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1407 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1408 xcpuid++;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1409 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1410 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1411
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1412 if (xcpuid) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1413 cp = &cpi->cpi_extd[0];
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1414 cp->cp_eax = 0x80000000;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1415 cpi->cpi_xmaxeax = __cpuid_insn(cp);
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1416 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1417
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1418 if (cpi->cpi_xmaxeax & 0x80000000) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1419
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1420 if (cpi->cpi_xmaxeax > CPI_XMAXEAX_MAX)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1421 cpi->cpi_xmaxeax = CPI_XMAXEAX_MAX;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1422
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1423 switch (cpi->cpi_vendor) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1424 case X86_VENDOR_Intel:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1425 case X86_VENDOR_AMD:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1426 if (cpi->cpi_xmaxeax < 0x80000001)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1427 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1428 cp = &cpi->cpi_extd[1];
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1429 cp->cp_eax = 0x80000001;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1430 (void) __cpuid_insn(cp);
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	1431
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1432 if (cpi->cpi_vendor == X86_VENDOR_AMD &&
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1433 cpi->cpi_family == 5 &&
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1434 cpi->cpi_model == 6 &&
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1435 cpi->cpi_step == 6) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1436 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1437 * K6 model 6 uses bit 10 to indicate SYSC
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1438 * Later models use bit 11. Fix it here.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1439 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1440 if (cp->cp_edx & 0x400) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1441 cp->cp_edx &= ~0x400;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1442 cp->cp_edx \|= CPUID_AMD_EDX_SYSC;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1443 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1444 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1445
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	1446 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000001, cp);
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	1447
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1448 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1449 * Compute the additions to the kernel's feature word.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1450 */
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1451 if (cp->cp_edx & CPUID_AMD_EDX_NX) {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1452 add_x86_feature(featureset, X86FSET_NX);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1453 }
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1454
7656 2621e50fdf4a PSARC 2008/382 Fast Reboot Sherry Moore <Sherry.Moore@Sun.COM> parents: 7589 diff changeset	1455 /*
2621e50fdf4a PSARC 2008/382 Fast Reboot Sherry Moore <Sherry.Moore@Sun.COM> parents: 7589 diff changeset	1456 * Regardless whether or not we boot 64-bit,
2621e50fdf4a PSARC 2008/382 Fast Reboot Sherry Moore <Sherry.Moore@Sun.COM> parents: 7589 diff changeset	1457 * we should have a way to identify whether
2621e50fdf4a PSARC 2008/382 Fast Reboot Sherry Moore <Sherry.Moore@Sun.COM> parents: 7589 diff changeset	1458 * the CPU is capable of running 64-bit.
2621e50fdf4a PSARC 2008/382 Fast Reboot Sherry Moore <Sherry.Moore@Sun.COM> parents: 7589 diff changeset	1459 */
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1460 if (cp->cp_edx & CPUID_AMD_EDX_LM) {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1461 add_x86_feature(featureset, X86FSET_64);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1462 }
7656 2621e50fdf4a PSARC 2008/382 Fast Reboot Sherry Moore <Sherry.Moore@Sun.COM> parents: 7589 diff changeset	1463
5349 01422ec04372 6453272 ctfmerge uses the largest pagesize from getpagesizes() which can be bad on systems with giant pages kchow parents: 5338 diff changeset	1464 #if defined(__amd64)
01422ec04372 6453272 ctfmerge uses the largest pagesize from getpagesizes() which can be bad on systems with giant pages kchow parents: 5338 diff changeset	1465 /* 1 GB large page - enable only for 64 bit kernel */
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1466 if (cp->cp_edx & CPUID_AMD_EDX_1GPG) {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1467 add_x86_feature(featureset, X86FSET_1GPG);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1468 }
5349 01422ec04372 6453272 ctfmerge uses the largest pagesize from getpagesizes() which can be bad on systems with giant pages kchow parents: 5338 diff changeset	1469 #endif
01422ec04372 6453272 ctfmerge uses the largest pagesize from getpagesizes() which can be bad on systems with giant pages kchow parents: 5338 diff changeset	1470
4628 f90cf8fd4710 6525798 Need Hardware Capabilities support for AMD Family 10h/sse4a processor kk208521 parents: 4606 diff changeset	1471 if ((cpi->cpi_vendor == X86_VENDOR_AMD) &&
f90cf8fd4710 6525798 Need Hardware Capabilities support for AMD Family 10h/sse4a processor kk208521 parents: 4606 diff changeset	1472 (cpi->cpi_std[1].cp_edx & CPUID_INTC_EDX_FXSR) &&
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1473 (cp->cp_ecx & CPUID_AMD_ECX_SSE4A)) {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1474 add_x86_feature(featureset, X86FSET_SSE4A);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1475 }
4628 f90cf8fd4710 6525798 Need Hardware Capabilities support for AMD Family 10h/sse4a processor kk208521 parents: 4606 diff changeset	1476
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1477 /*
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	1478 * If both the HTT and CMP_LGCY bits are set,
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1479 * then we're not actually HyperThreaded. Read
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1480 * "AMD CPUID Specification" for more details.
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1481 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1482 if (cpi->cpi_vendor == X86_VENDOR_AMD &&
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1483 is_x86_feature(featureset, X86FSET_HTT) &&
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	1484 (cp->cp_ecx & CPUID_AMD_ECX_CMP_LGCY)) {
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1485 remove_x86_feature(featureset, X86FSET_HTT);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1486 add_x86_feature(featureset, X86FSET_CMP);
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1487 }
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	1488 #if defined(__amd64)
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1489 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1490 * It's really tricky to support syscall/sysret in
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1491 * the i386 kernel; we rely on sysenter/sysexit
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1492 * instead. In the amd64 kernel, things are -way-
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1493 * better.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1494 */
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1495 if (cp->cp_edx & CPUID_AMD_EDX_SYSC) {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1496 add_x86_feature(featureset, X86FSET_ASYSC);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1497 }
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1498
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1499 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1500 * While we're thinking about system calls, note
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1501 * that AMD processors don't support sysenter
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1502 * in long mode at all, so don't try to program them.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1503 */
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1504 if (x86_vendor == X86_VENDOR_AMD) {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1505 remove_x86_feature(featureset, X86FSET_SEP);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1506 }
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1507 #endif
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1508 if (cp->cp_edx & CPUID_AMD_EDX_TSCP) {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1509 add_x86_feature(featureset, X86FSET_TSCP);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1510 }
13425 8640246a3548 1347 isainfo should indicate presence of vmx/svm support Bryan Cantrill <bryan@joyent.com> parents: 13148 diff changeset	1511
8640246a3548 1347 isainfo should indicate presence of vmx/svm support Bryan Cantrill <bryan@joyent.com> parents: 13148 diff changeset	1512 if (cp->cp_ecx & CPUID_AMD_ECX_SVM) {
8640246a3548 1347 isainfo should indicate presence of vmx/svm support Bryan Cantrill <bryan@joyent.com> parents: 13148 diff changeset	1513 add_x86_feature(featureset, X86FSET_SVM);
8640246a3548 1347 isainfo should indicate presence of vmx/svm support Bryan Cantrill <bryan@joyent.com> parents: 13148 diff changeset	1514 }
13681 73253247f9e5 2650 AMD family 0x15 PG support Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13675 diff changeset	1515
73253247f9e5 2650 AMD family 0x15 PG support Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13675 diff changeset	1516 if (cp->cp_ecx & CPUID_AMD_ECX_TOPOEXT) {
73253247f9e5 2650 AMD family 0x15 PG support Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13675 diff changeset	1517 add_x86_feature(featureset, X86FSET_TOPOEXT);
73253247f9e5 2650 AMD family 0x15 PG support Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13675 diff changeset	1518 }
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1519 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1520 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1521 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1522 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1523
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1524 /*
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1525 * Get CPUID data about processor cores and hyperthreads.
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1526 */
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1527 switch (cpi->cpi_vendor) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1528 case X86_VENDOR_Intel:
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1529 if (cpi->cpi_maxeax >= 4) {
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1530 cp = &cpi->cpi_std[4];
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1531 cp->cp_eax = 4;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1532 cp->cp_ecx = 0;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1533 (void) __cpuid_insn(cp);
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	1534 platform_cpuid_mangle(cpi->cpi_vendor, 4, cp);
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1535 }
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1536 /FALLTHROUGH/
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1537 case X86_VENDOR_AMD:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1538 if (cpi->cpi_xmaxeax < 0x80000008)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1539 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1540 cp = &cpi->cpi_extd[8];
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1541 cp->cp_eax = 0x80000008;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1542 (void) __cpuid_insn(cp);
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	1543 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000008, cp);
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	1544
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1545 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1546 * Virtual and physical address limits from
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1547 * cpuid override previously guessed values.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1548 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1549 cpi->cpi_pabits = BITX(cp->cp_eax, 7, 0);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1550 cpi->cpi_vabits = BITX(cp->cp_eax, 15, 8);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1551 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1552 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1553 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1554 }
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1555
4606 ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1556 /*
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1557 * Derive the number of cores per chip
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1558 */
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1559 switch (cpi->cpi_vendor) {
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1560 case X86_VENDOR_Intel:
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1561 if (cpi->cpi_maxeax < 4) {
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1562 cpi->cpi_ncore_per_chip = 1;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1563 break;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1564 } else {
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1565 cpi->cpi_ncore_per_chip =
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1566 BITX((cpi)->cpi_std[4].cp_eax, 31, 26) + 1;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1567 }
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1568 break;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1569 case X86_VENDOR_AMD:
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1570 if (cpi->cpi_xmaxeax < 0x80000008) {
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1571 cpi->cpi_ncore_per_chip = 1;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1572 break;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1573 } else {
5870 2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	1574 /*
2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	1575 * On family 0xf cpuid fn 2 ECX[7:0] "NC" is
2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	1576 * 1 less than the number of physical cores on
2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	1577 * the chip. In family 0x10 this value can
2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	1578 * be affected by "downcoring" - it reflects
2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	1579 * 1 less than the number of cores actually
2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	1580 * enabled on this node.
2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	1581 */
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1582 cpi->cpi_ncore_per_chip =
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1583 BITX((cpi)->cpi_extd[8].cp_ecx, 7, 0) + 1;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1584 }
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1585 break;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1586 default:
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1587 cpi->cpi_ncore_per_chip = 1;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1588 break;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1589 }
8906 e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	1590
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	1591 /*
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	1592 * Get CPUID data about TSC Invariance in Deep C-State.
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	1593 */
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	1594 switch (cpi->cpi_vendor) {
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	1595 case X86_VENDOR_Intel:
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	1596 if (cpi->cpi_maxeax >= 7) {
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	1597 cp = &cpi->cpi_extd[7];
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	1598 cp->cp_eax = 0x80000007;
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	1599 cp->cp_ecx = 0;
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	1600 (void) __cpuid_insn(cp);
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	1601 }
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	1602 break;
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	1603 default:
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	1604 break;
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	1605 }
5284 2f7098179999 6617465 Pentium IIIs die with divide error trap gavinm parents: 5269 diff changeset	1606 } else {
2f7098179999 6617465 Pentium IIIs die with divide error trap gavinm parents: 5269 diff changeset	1607 cpi->cpi_ncore_per_chip = 1;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1608 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1609
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1610 /*
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1611 * If more than one core, then this processor is CMP.
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1612 */
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1613 if (cpi->cpi_ncore_per_chip > 1) {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1614 add_x86_feature(featureset, X86FSET_CMP);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1615 }
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	1616
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1617 /*
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1618 * If the number of cores is the same as the number
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1619 * of CPUs, then we cannot have HyperThreading.
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1620 */
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1621 if (cpi->cpi_ncpu_per_chip == cpi->cpi_ncore_per_chip) {
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1622 remove_x86_feature(featureset, X86FSET_HTT);
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1623 }
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1624
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	1625 cpi->cpi_apicid = CPI_APIC_ID(cpi);
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	1626 cpi->cpi_procnodes_per_pkg = 1;
13681 73253247f9e5 2650 AMD family 0x15 PG support Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13675 diff changeset	1627 cpi->cpi_cores_per_compunit = 1;
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1628 if (is_x86_feature(featureset, X86FSET_HTT) == B_FALSE &&
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1629 is_x86_feature(featureset, X86FSET_CMP) == B_FALSE) {
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1630 /*
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1631 * Single-core single-threaded processors.
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1632 */
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1633 cpi->cpi_chipid = -1;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1634 cpi->cpi_clogid = 0;
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1635 cpi->cpi_coreid = cpu->cpu_id;
5870 2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	1636 cpi->cpi_pkgcoreid = 0;
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	1637 if (cpi->cpi_vendor == X86_VENDOR_AMD)
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	1638 cpi->cpi_procnodeid = BITX(cpi->cpi_apicid, 3, 0);
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	1639 else
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	1640 cpi->cpi_procnodeid = cpi->cpi_chipid;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1641 } else if (cpi->cpi_ncpu_per_chip > 1) {
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	1642 if (cpi->cpi_vendor == X86_VENDOR_Intel)
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	1643 cpuid_intel_getids(cpu, featureset);
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	1644 else if (cpi->cpi_vendor == X86_VENDOR_AMD)
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	1645 cpuid_amd_getids(cpu);
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	1646 else {
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1647 /*
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1648 * All other processors are currently
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1649 * assumed to have single cores.
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1650 */
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1651 cpi->cpi_coreid = cpi->cpi_chipid;
5870 2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	1652 cpi->cpi_pkgcoreid = 0;
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	1653 cpi->cpi_procnodeid = cpi->cpi_chipid;
13681 73253247f9e5 2650 AMD family 0x15 PG support Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13675 diff changeset	1654 cpi->cpi_compunitid = cpi->cpi_chipid;
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1655 }
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1656 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1657
2869 324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	1658 /*
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	1659 * Synthesize chip "revision" and socket type
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	1660 */
7532 bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	1661 cpi->cpi_chiprev = _cpuid_chiprev(cpi->cpi_vendor, cpi->cpi_family,
bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	1662 cpi->cpi_model, cpi->cpi_step);
bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	1663 cpi->cpi_chiprevstr = _cpuid_chiprevstr(cpi->cpi_vendor,
bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	1664 cpi->cpi_family, cpi->cpi_model, cpi->cpi_step);
bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	1665 cpi->cpi_socket = _cpuid_skt(cpi->cpi_vendor, cpi->cpi_family,
bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	1666 cpi->cpi_model, cpi->cpi_step);
2869 324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	1667
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1668 pass1_done:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1669 cpi->cpi_pass = 1;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1670 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1671
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1672 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1673 * Make copies of the cpuid table entries we depend on, in
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1674 * part for ease of parsing now, in part so that we have only
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1675 * one place to correct any of it, in part for ease of
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1676 * later export to userland, and in part so we can look at
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1677 * this stuff in a crash dump.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1678 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1679
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1680 /ARGSUSED/
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1681 void
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1682 cpuid_pass2(cpu_t *cpu)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1683 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1684 uint_t n, nmax;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1685 int i;
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1686 struct cpuid_regs *cp;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1687 uint8_t *dp;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1688 uint32_t *iptr;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1689 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1690
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1691 ASSERT(cpi->cpi_pass == 1);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1692
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1693 if (cpi->cpi_maxeax < 1)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1694 goto pass2_done;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1695
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1696 if ((nmax = cpi->cpi_maxeax + 1) > NMAX_CPI_STD)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1697 nmax = NMAX_CPI_STD;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1698 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1699 * (We already handled n == 0 and n == 1 in pass 1)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1700 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1701 for (n = 2, cp = &cpi->cpi_std[2]; n < nmax; n++, cp++) {
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1702 cp->cp_eax = n;
4606 ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1703
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1704 /*
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1705 * CPUID function 4 expects %ecx to be initialized
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1706 * with an index which indicates which cache to return
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1707 * information about. The OS is expected to call function 4
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1708 * with %ecx set to 0, 1, 2, ... until it returns with
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1709 * EAX[4:0] set to 0, which indicates there are no more
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1710 * caches.
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1711 *
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1712 * Here, populate cpi_std[4] with the information returned by
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1713 * function 4 when %ecx == 0, and do the rest in cpuid_pass3()
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1714 * when dynamic memory allocation becomes available.
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1715 *
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1716 * Note: we need to explicitly initialize %ecx here, since
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1717 * function 4 may have been previously invoked.
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1718 */
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1719 if (n == 4)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1720 cp->cp_ecx = 0;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	1721
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1722 (void) __cpuid_insn(cp);
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	1723 platform_cpuid_mangle(cpi->cpi_vendor, n, cp);
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1724 switch (n) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1725 case 2:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1726 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1727 * "the lower 8 bits of the %eax register
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1728 * contain a value that identifies the number
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1729 * of times the cpuid [instruction] has to be
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1730 * executed to obtain a complete image of the
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1731 * processor's caching systems."
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1732 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1733 * How do they make this stuff up?
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1734 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1735 cpi->cpi_ncache = sizeof (cp)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1736 BITX(cp->cp_eax, 7, 0);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1737 if (cpi->cpi_ncache == 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1738 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1739 cpi->cpi_ncache--; /* skip count byte */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1740
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1741 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1742 * Well, for now, rather than attempt to implement
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1743 * this slightly dubious algorithm, we just look
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1744 * at the first 15 ..
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1745 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1746 if (cpi->cpi_ncache > (sizeof (*cp) - 1))
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1747 cpi->cpi_ncache = sizeof (*cp) - 1;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1748
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1749 dp = cpi->cpi_cacheinfo;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1750 if (BITX(cp->cp_eax, 31, 31) == 0) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1751 uint8_t p = (void )&cp->cp_eax;
6317 8afb524fc268 6667600 Incomplete initialization of cpi_cacheinfo field of struct cpuid_info kk208521 parents: 5870 diff changeset	1752 for (i = 1; i < 4; i++)
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1753 if (p[i] != 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1754 *dp++ = p[i];
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1755 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1756 if (BITX(cp->cp_ebx, 31, 31) == 0) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1757 uint8_t p = (void )&cp->cp_ebx;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1758 for (i = 0; i < 4; i++)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1759 if (p[i] != 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1760 *dp++ = p[i];
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1761 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1762 if (BITX(cp->cp_ecx, 31, 31) == 0) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1763 uint8_t p = (void )&cp->cp_ecx;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1764 for (i = 0; i < 4; i++)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1765 if (p[i] != 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1766 *dp++ = p[i];
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1767 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1768 if (BITX(cp->cp_edx, 31, 31) == 0) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1769 uint8_t p = (void )&cp->cp_edx;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1770 for (i = 0; i < 4; i++)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1771 if (p[i] != 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1772 *dp++ = p[i];
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1773 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1774 break;
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1775
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1776 case 3: /* Processor serial number, if PSN supported */
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1777 break;
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1778
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1779 case 4: /* Deterministic cache parameters */
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1780 break;
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1781
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1782 case 5: /* Monitor/Mwait parameters */
5045 75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1783 {
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1784 size_t mwait_size;
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1785
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1786 /*
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1787 * check cpi_mwait.support which was set in cpuid_pass1
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1788 */
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1789 if (!(cpi->cpi_mwait.support & MWAIT_SUPPORT))
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1790 break;
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1791
5045 75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1792 /*
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1793 * Protect ourself from insane mwait line size.
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1794 * Workaround for incomplete hardware emulator(s).
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1795 */
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1796 mwait_size = (size_t)MWAIT_SIZE_MAX(cpi);
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1797 if (mwait_size < sizeof (uint32_t) \|\|
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1798 !ISP2(mwait_size)) {
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1799 #if DEBUG
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1800 cmn_err(CE_NOTE, "Cannot handle cpu %d mwait "
7798 2a682532f0ca 6749646 cpuid_pass2 stomps on cpi_xmaxeax Saurabh Misra <Saurabh.Mishra@Sun.COM> parents: 7716 diff changeset	1801 "size %ld", cpu->cpu_id, (long)mwait_size);
5045 75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1802 #endif
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1803 break;
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1804 }
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1805
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1806 cpi->cpi_mwait.mon_min = (size_t)MWAIT_SIZE_MIN(cpi);
5045 75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1807 cpi->cpi_mwait.mon_max = mwait_size;
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1808 if (MWAIT_EXTENSION(cpi)) {
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1809 cpi->cpi_mwait.support \|= MWAIT_EXTENSIONS;
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1810 if (MWAIT_INT_ENABLE(cpi))
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1811 cpi->cpi_mwait.support \|=
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1812 MWAIT_ECX_INT_ENABLE;
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1813 }
2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	1814 break;
5045 75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	1815 }
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1816 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1817 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1818 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1819 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1820
7282 5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1821 if (cpi->cpi_maxeax >= 0xB && cpi->cpi_vendor == X86_VENDOR_Intel) {
7798 2a682532f0ca 6749646 cpuid_pass2 stomps on cpi_xmaxeax Saurabh Misra <Saurabh.Mishra@Sun.COM> parents: 7716 diff changeset	1822 struct cpuid_regs regs;
2a682532f0ca 6749646 cpuid_pass2 stomps on cpi_xmaxeax Saurabh Misra <Saurabh.Mishra@Sun.COM> parents: 7716 diff changeset	1823
2a682532f0ca 6749646 cpuid_pass2 stomps on cpi_xmaxeax Saurabh Misra <Saurabh.Mishra@Sun.COM> parents: 7716 diff changeset	1824 cp = &regs;
7282 5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1825 cp->cp_eax = 0xB;
7798 2a682532f0ca 6749646 cpuid_pass2 stomps on cpi_xmaxeax Saurabh Misra <Saurabh.Mishra@Sun.COM> parents: 7716 diff changeset	1826 cp->cp_edx = cp->cp_ebx = cp->cp_ecx = 0;
7282 5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1827
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1828 (void) __cpuid_insn(cp);
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1829
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1830 /*
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1831 * Check CPUID.EAX=0BH, ECX=0H:EBX is non-zero, which
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1832 * indicates that the extended topology enumeration leaf is
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1833 * available.
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1834 */
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1835 if (cp->cp_ebx) {
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1836 uint32_t x2apic_id;
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1837 uint_t coreid_shift = 0;
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1838 uint_t ncpu_per_core = 1;
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1839 uint_t chipid_shift = 0;
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1840 uint_t ncpu_per_chip = 1;
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1841 uint_t i;
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1842 uint_t level;
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1843
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1844 for (i = 0; i < CPI_FNB_ECX_MAX; i++) {
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1845 cp->cp_eax = 0xB;
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1846 cp->cp_ecx = i;
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1847
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1848 (void) __cpuid_insn(cp);
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1849 level = CPI_CPU_LEVEL_TYPE(cp);
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1850
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1851 if (level == 1) {
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1852 x2apic_id = cp->cp_edx;
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1853 coreid_shift = BITX(cp->cp_eax, 4, 0);
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1854 ncpu_per_core = BITX(cp->cp_ebx, 15, 0);
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1855 } else if (level == 2) {
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1856 x2apic_id = cp->cp_edx;
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1857 chipid_shift = BITX(cp->cp_eax, 4, 0);
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1858 ncpu_per_chip = BITX(cp->cp_ebx, 15, 0);
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1859 }
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1860 }
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1861
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1862 cpi->cpi_apicid = x2apic_id;
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1863 cpi->cpi_ncpu_per_chip = ncpu_per_chip;
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1864 cpi->cpi_ncore_per_chip = ncpu_per_chip /
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1865 ncpu_per_core;
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1866 cpi->cpi_chipid = x2apic_id >> chipid_shift;
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1867 cpi->cpi_clogid = x2apic_id & ((1 << chipid_shift) - 1);
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1868 cpi->cpi_coreid = x2apic_id >> coreid_shift;
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1869 cpi->cpi_pkgcoreid = cpi->cpi_clogid >> coreid_shift;
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1870 }
7798 2a682532f0ca 6749646 cpuid_pass2 stomps on cpi_xmaxeax Saurabh Misra <Saurabh.Mishra@Sun.COM> parents: 7716 diff changeset	1871
2a682532f0ca 6749646 cpuid_pass2 stomps on cpi_xmaxeax Saurabh Misra <Saurabh.Mishra@Sun.COM> parents: 7716 diff changeset	1872 /* Make cp NULL so that we don't stumble on others */
2a682532f0ca 6749646 cpuid_pass2 stomps on cpi_xmaxeax Saurabh Misra <Saurabh.Mishra@Sun.COM> parents: 7716 diff changeset	1873 cp = NULL;
7282 5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1874 }
5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	1875
13146 8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1876 /*
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1877 * XSAVE enumeration
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1878 */
13655 0461a7e94e53 2412 Various CPU features aren't intel specific Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13651 diff changeset	1879 if (cpi->cpi_maxeax >= 0xD) {
13146 8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1880 struct cpuid_regs regs;
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1881 boolean_t cpuid_d_valid = B_TRUE;
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1882
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1883 cp = &regs;
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1884 cp->cp_eax = 0xD;
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1885 cp->cp_edx = cp->cp_ebx = cp->cp_ecx = 0;
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1886
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1887 (void) __cpuid_insn(cp);
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1888
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1889 /*
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1890 * Sanity checks for debug
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1891 */
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1892 if ((cp->cp_eax & XFEATURE_LEGACY_FP) == 0 \|\|
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1893 (cp->cp_eax & XFEATURE_SSE) == 0) {
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1894 cpuid_d_valid = B_FALSE;
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1895 }
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1896
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1897 cpi->cpi_xsave.xsav_hw_features_low = cp->cp_eax;
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1898 cpi->cpi_xsave.xsav_hw_features_high = cp->cp_edx;
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1899 cpi->cpi_xsave.xsav_max_size = cp->cp_ecx;
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1900
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1901 /*
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1902 * If the hw supports AVX, get the size and offset in the save
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1903 * area for the ymm state.
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1904 */
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1905 if (cpi->cpi_xsave.xsav_hw_features_low & XFEATURE_AVX) {
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1906 cp->cp_eax = 0xD;
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1907 cp->cp_ecx = 2;
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1908 cp->cp_edx = cp->cp_ebx = 0;
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1909
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1910 (void) __cpuid_insn(cp);
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1911
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1912 if (cp->cp_ebx != CPUID_LEAFD_2_YMM_OFFSET \|\|
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1913 cp->cp_eax != CPUID_LEAFD_2_YMM_SIZE) {
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1914 cpuid_d_valid = B_FALSE;
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1915 }
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1916
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1917 cpi->cpi_xsave.ymm_size = cp->cp_eax;
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1918 cpi->cpi_xsave.ymm_offset = cp->cp_ebx;
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1919 }
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1920
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1921 if (is_x86_feature(x86_featureset, X86FSET_XSAVE)) {
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1922 xsave_state_size = 0;
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1923 } else if (cpuid_d_valid) {
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1924 xsave_state_size = cpi->cpi_xsave.xsav_max_size;
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1925 } else {
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1926 /* Broken CPUID 0xD, probably in HVM */
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1927 cmn_err(CE_WARN, "cpu%d: CPUID.0xD returns invalid "
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1928 "value: hw_low = %d, hw_high = %d, xsave_size = %d"
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1929 ", ymm_size = %d, ymm_offset = %d\n",
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1930 cpu->cpu_id, cpi->cpi_xsave.xsav_hw_features_low,
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1931 cpi->cpi_xsave.xsav_hw_features_high,
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1932 (int)cpi->cpi_xsave.xsav_max_size,
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1933 (int)cpi->cpi_xsave.ymm_size,
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1934 (int)cpi->cpi_xsave.ymm_offset);
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1935
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1936 if (xsave_state_size != 0) {
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1937 /*
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1938 * This must be a non-boot CPU. We cannot
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1939 * continue, because boot cpu has already
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1940 * enabled XSAVE.
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1941 */
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1942 ASSERT(cpu->cpu_id != 0);
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1943 cmn_err(CE_PANIC, "cpu%d: we have already "
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1944 "enabled XSAVE on boot cpu, cannot "
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1945 "continue.", cpu->cpu_id);
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1946 } else {
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1947 /*
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1948 * Must be from boot CPU, OK to disable XSAVE.
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1949 */
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1950 ASSERT(cpu->cpu_id == 0);
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1951 remove_x86_feature(x86_featureset,
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1952 X86FSET_XSAVE);
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1953 remove_x86_feature(x86_featureset, X86FSET_AVX);
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1954 CPI_FEATURES_ECX(cpi) &= ~CPUID_INTC_ECX_XSAVE;
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1955 CPI_FEATURES_ECX(cpi) &= ~CPUID_INTC_ECX_AVX;
13905 b151bd260b71 3414 Need a new word of AT_SUN_HWCAP bits Robert Mustacchi <rm@joyent.com> parents: 13681 diff changeset	1956 CPI_FEATURES_ECX(cpi) &= ~CPUID_INTC_ECX_F16C;
13146 8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1957 xsave_force_disable = B_TRUE;
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1958 }
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1959 }
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1960 }
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1961
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	1962
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1963 if ((cpi->cpi_xmaxeax & 0x80000000) == 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1964 goto pass2_done;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1965
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1966 if ((nmax = cpi->cpi_xmaxeax - 0x80000000 + 1) > NMAX_CPI_EXTD)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1967 nmax = NMAX_CPI_EXTD;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1968 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1969 * Copy the extended properties, fixing them as we go.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1970 * (We already handled n == 0 and n == 1 in pass 1)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1971 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1972 iptr = (void *)cpi->cpi_brandstr;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1973 for (n = 2, cp = &cpi->cpi_extd[2]; n < nmax; cp++, n++) {
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1974 cp->cp_eax = 0x80000000 + n;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	1975 (void) __cpuid_insn(cp);
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	1976 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000000 + n, cp);
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1977 switch (n) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1978 case 2:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1979 case 3:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1980 case 4:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1981 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1982 * Extract the brand string
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1983 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1984 *iptr++ = cp->cp_eax;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1985 *iptr++ = cp->cp_ebx;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1986 *iptr++ = cp->cp_ecx;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1987 *iptr++ = cp->cp_edx;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1988 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1989 case 5:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1990 switch (cpi->cpi_vendor) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1991 case X86_VENDOR_AMD:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1992 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1993 * The Athlon and Duron were the first
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1994 * parts to report the sizes of the
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1995 * TLB for large pages. Before then,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1996 * we don't trust the data.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1997 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1998 if (cpi->cpi_family < 6 \|\|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	1999 (cpi->cpi_family == 6 &&
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2000 cpi->cpi_model < 1))
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2001 cp->cp_eax = 0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2002 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2003 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2004 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2005 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2006 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2007 case 6:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2008 switch (cpi->cpi_vendor) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2009 case X86_VENDOR_AMD:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2010 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2011 * The Athlon and Duron were the first
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2012 * AMD parts with L2 TLB's.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2013 * Before then, don't trust the data.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2014 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2015 if (cpi->cpi_family < 6 \|\|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2016 cpi->cpi_family == 6 &&
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2017 cpi->cpi_model < 1)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2018 cp->cp_eax = cp->cp_ebx = 0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2019 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2020 * AMD Duron rev A0 reports L2
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2021 * cache size incorrectly as 1K
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2022 * when it is really 64K
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2023 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2024 if (cpi->cpi_family == 6 &&
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2025 cpi->cpi_model == 3 &&
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2026 cpi->cpi_step == 0) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2027 cp->cp_ecx &= 0xffff;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2028 cp->cp_ecx \|= 0x400000;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2029 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2030 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2031 case X86_VENDOR_Cyrix: /* VIA C3 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2032 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2033 * VIA C3 processors are a bit messed
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2034 * up w.r.t. encoding cache sizes in %ecx
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2035 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2036 if (cpi->cpi_family != 6)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2037 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2038 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2039 * model 7 and 8 were incorrectly encoded
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2040 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2041 * xxx is model 8 really broken?
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2042 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2043 if (cpi->cpi_model == 7 \|\|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2044 cpi->cpi_model == 8)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2045 cp->cp_ecx =
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2046 BITX(cp->cp_ecx, 31, 24) << 16 \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2047 BITX(cp->cp_ecx, 23, 16) << 12 \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2048 BITX(cp->cp_ecx, 15, 8) << 8 \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2049 BITX(cp->cp_ecx, 7, 0);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2050 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2051 * model 9 stepping 1 has wrong associativity
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2052 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2053 if (cpi->cpi_model == 9 && cpi->cpi_step == 1)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2054 cp->cp_ecx \|= 8 << 12;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2055 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2056 case X86_VENDOR_Intel:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2057 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2058 * Extended L2 Cache features function.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2059 * First appeared on Prescott.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2060 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2061 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2062 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2063 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2064 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2065 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2066 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2067 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2068 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2069
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2070 pass2_done:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2071 cpi->cpi_pass = 2;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2072 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2073
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2074 static const char *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2075 intel_cpubrand(const struct cpuid_info *cpi)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2076 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2077 int i;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2078
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	2079 if (!is_x86_feature(x86_featureset, X86FSET_CPUID) \|\|
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2080 cpi->cpi_maxeax < 1 \|\| cpi->cpi_family < 5)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2081 return ("i486");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2082
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2083 switch (cpi->cpi_family) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2084 case 5:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2085 return ("Intel Pentium(r)");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2086 case 6:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2087 switch (cpi->cpi_model) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2088 uint_t celeron, xeon;
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2089 const struct cpuid_regs *cp;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2090 case 0:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2091 case 1:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2092 case 2:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2093 return ("Intel Pentium(r) Pro");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2094 case 3:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2095 case 4:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2096 return ("Intel Pentium(r) II");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2097 case 6:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2098 return ("Intel Celeron(r)");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2099 case 5:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2100 case 7:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2101 celeron = xeon = 0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2102 cp = &cpi->cpi_std[2]; /* cache info */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2103
6317 8afb524fc268 6667600 Incomplete initialization of cpi_cacheinfo field of struct cpuid_info kk208521 parents: 5870 diff changeset	2104 for (i = 1; i < 4; i++) {
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2105 uint_t tmp;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2106
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2107 tmp = (cp->cp_eax >> (8 * i)) & 0xff;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2108 if (tmp == 0x40)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2109 celeron++;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2110 if (tmp >= 0x44 && tmp <= 0x45)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2111 xeon++;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2112 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2113
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2114 for (i = 0; i < 2; i++) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2115 uint_t tmp;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2116
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2117 tmp = (cp->cp_ebx >> (8 * i)) & 0xff;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2118 if (tmp == 0x40)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2119 celeron++;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2120 else if (tmp >= 0x44 && tmp <= 0x45)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2121 xeon++;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2122 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2123
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2124 for (i = 0; i < 4; i++) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2125 uint_t tmp;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2126
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2127 tmp = (cp->cp_ecx >> (8 * i)) & 0xff;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2128 if (tmp == 0x40)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2129 celeron++;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2130 else if (tmp >= 0x44 && tmp <= 0x45)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2131 xeon++;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2132 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2133
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2134 for (i = 0; i < 4; i++) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2135 uint_t tmp;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2136
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2137 tmp = (cp->cp_edx >> (8 * i)) & 0xff;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2138 if (tmp == 0x40)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2139 celeron++;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2140 else if (tmp >= 0x44 && tmp <= 0x45)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2141 xeon++;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2142 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2143
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2144 if (celeron)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2145 return ("Intel Celeron(r)");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2146 if (xeon)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2147 return (cpi->cpi_model == 5 ?
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2148 "Intel Pentium(r) II Xeon(tm)" :
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2149 "Intel Pentium(r) III Xeon(tm)");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2150 return (cpi->cpi_model == 5 ?
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2151 "Intel Pentium(r) II or Pentium(r) II Xeon(tm)" :
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2152 "Intel Pentium(r) III or Pentium(r) III Xeon(tm)");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2153 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2154 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2155 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2156 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2157 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2158 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2159
1975 7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	2160 /* BrandID is present if the field is nonzero */
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	2161 if (cpi->cpi_brandid != 0) {
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2162 static const struct {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2163 uint_t bt_bid;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2164 const char *bt_str;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2165 } brand_tbl[] = {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2166 { 0x1, "Intel(r) Celeron(r)" },
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2167 { 0x2, "Intel(r) Pentium(r) III" },
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2168 { 0x3, "Intel(r) Pentium(r) III Xeon(tm)" },
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2169 { 0x4, "Intel(r) Pentium(r) III" },
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2170 { 0x6, "Mobile Intel(r) Pentium(r) III" },
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2171 { 0x7, "Mobile Intel(r) Celeron(r)" },
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2172 { 0x8, "Intel(r) Pentium(r) 4" },
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2173 { 0x9, "Intel(r) Pentium(r) 4" },
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2174 { 0xa, "Intel(r) Celeron(r)" },
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2175 { 0xb, "Intel(r) Xeon(tm)" },
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2176 { 0xc, "Intel(r) Xeon(tm) MP" },
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2177 { 0xe, "Mobile Intel(r) Pentium(r) 4" },
1975 7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	2178 { 0xf, "Mobile Intel(r) Celeron(r)" },
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	2179 { 0x11, "Mobile Genuine Intel(r)" },
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	2180 { 0x12, "Intel(r) Celeron(r) M" },
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	2181 { 0x13, "Mobile Intel(r) Celeron(r)" },
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	2182 { 0x14, "Intel(r) Celeron(r)" },
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	2183 { 0x15, "Mobile Genuine Intel(r)" },
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	2184 { 0x16, "Intel(r) Pentium(r) M" },
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	2185 { 0x17, "Mobile Intel(r) Celeron(r)" }
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2186 };
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2187 uint_t btblmax = sizeof (brand_tbl) / sizeof (brand_tbl[0]);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2188 uint_t sgn;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2189
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2190 sgn = (cpi->cpi_family << 8) \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2191 (cpi->cpi_model << 4) \| cpi->cpi_step;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2192
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2193 for (i = 0; i < btblmax; i++)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2194 if (brand_tbl[i].bt_bid == cpi->cpi_brandid)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2195 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2196 if (i < btblmax) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2197 if (sgn == 0x6b1 && cpi->cpi_brandid == 3)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2198 return ("Intel(r) Celeron(r)");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2199 if (sgn < 0xf13 && cpi->cpi_brandid == 0xb)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2200 return ("Intel(r) Xeon(tm) MP");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2201 if (sgn < 0xf13 && cpi->cpi_brandid == 0xe)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2202 return ("Intel(r) Xeon(tm)");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2203 return (brand_tbl[i].bt_str);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2204 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2205 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2206
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2207 return (NULL);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2208 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2209
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2210 static const char *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2211 amd_cpubrand(const struct cpuid_info *cpi)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2212 {
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	2213 if (!is_x86_feature(x86_featureset, X86FSET_CPUID) \|\|
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2214 cpi->cpi_maxeax < 1 \|\| cpi->cpi_family < 5)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2215 return ("i486 compatible");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2216
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2217 switch (cpi->cpi_family) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2218 case 5:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2219 switch (cpi->cpi_model) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2220 case 0:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2221 case 1:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2222 case 2:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2223 case 3:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2224 case 4:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2225 case 5:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2226 return ("AMD-K5(r)");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2227 case 6:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2228 case 7:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2229 return ("AMD-K6(r)");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2230 case 8:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2231 return ("AMD-K6(r)-2");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2232 case 9:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2233 return ("AMD-K6(r)-III");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2234 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2235 return ("AMD (family 5)");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2236 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2237 case 6:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2238 switch (cpi->cpi_model) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2239 case 1:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2240 return ("AMD-K7(tm)");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2241 case 0:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2242 case 2:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2243 case 4:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2244 return ("AMD Athlon(tm)");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2245 case 3:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2246 case 7:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2247 return ("AMD Duron(tm)");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2248 case 6:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2249 case 8:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2250 case 10:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2251 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2252 * Use the L2 cache size to distinguish
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2253 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2254 return ((cpi->cpi_extd[6].cp_ecx >> 16) >= 256 ?
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2255 "AMD Athlon(tm)" : "AMD Duron(tm)");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2256 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2257 return ("AMD (family 6)");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2258 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2259 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2260 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2261 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2262
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2263 if (cpi->cpi_family == 0xf && cpi->cpi_model == 5 &&
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2264 cpi->cpi_brandid != 0) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2265 switch (BITX(cpi->cpi_brandid, 7, 5)) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2266 case 3:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2267 return ("AMD Opteron(tm) UP 1xx");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2268 case 4:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2269 return ("AMD Opteron(tm) DP 2xx");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2270 case 5:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2271 return ("AMD Opteron(tm) MP 8xx");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2272 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2273 return ("AMD Opteron(tm)");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2274 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2275 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2276
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2277 return (NULL);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2278 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2279
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2280 static const char *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2281 cyrix_cpubrand(struct cpuid_info *cpi, uint_t type)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2282 {
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	2283 if (!is_x86_feature(x86_featureset, X86FSET_CPUID) \|\|
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2284 cpi->cpi_maxeax < 1 \|\| cpi->cpi_family < 5 \|\|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2285 type == X86_TYPE_CYRIX_486)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2286 return ("i486 compatible");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2287
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2288 switch (type) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2289 case X86_TYPE_CYRIX_6x86:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2290 return ("Cyrix 6x86");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2291 case X86_TYPE_CYRIX_6x86L:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2292 return ("Cyrix 6x86L");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2293 case X86_TYPE_CYRIX_6x86MX:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2294 return ("Cyrix 6x86MX");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2295 case X86_TYPE_CYRIX_GXm:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2296 return ("Cyrix GXm");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2297 case X86_TYPE_CYRIX_MediaGX:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2298 return ("Cyrix MediaGX");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2299 case X86_TYPE_CYRIX_MII:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2300 return ("Cyrix M2");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2301 case X86_TYPE_VIA_CYRIX_III:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2302 return ("VIA Cyrix M3");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2303 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2304 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2305 * Have another wild guess ..
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2306 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2307 if (cpi->cpi_family == 4 && cpi->cpi_model == 9)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2308 return ("Cyrix 5x86");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2309 else if (cpi->cpi_family == 5) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2310 switch (cpi->cpi_model) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2311 case 2:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2312 return ("Cyrix 6x86"); /* Cyrix M1 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2313 case 4:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2314 return ("Cyrix MediaGX");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2315 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2316 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2317 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2318 } else if (cpi->cpi_family == 6) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2319 switch (cpi->cpi_model) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2320 case 0:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2321 return ("Cyrix 6x86MX"); /* Cyrix M2? */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2322 case 5:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2323 case 6:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2324 case 7:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2325 case 8:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2326 case 9:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2327 return ("VIA C3");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2328 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2329 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2330 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2331 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2332 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2333 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2334 return (NULL);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2335 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2336
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2337 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2338 * This only gets called in the case that the CPU extended
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2339 * feature brand string (0x80000002, 0x80000003, 0x80000004)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2340 * aren't available, or contain null bytes for some reason.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2341 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2342 static void
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2343 fabricate_brandstr(struct cpuid_info *cpi)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2344 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2345 const char *brand = NULL;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2346
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2347 switch (cpi->cpi_vendor) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2348 case X86_VENDOR_Intel:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2349 brand = intel_cpubrand(cpi);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2350 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2351 case X86_VENDOR_AMD:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2352 brand = amd_cpubrand(cpi);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2353 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2354 case X86_VENDOR_Cyrix:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2355 brand = cyrix_cpubrand(cpi, x86_type);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2356 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2357 case X86_VENDOR_NexGen:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2358 if (cpi->cpi_family == 5 && cpi->cpi_model == 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2359 brand = "NexGen Nx586";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2360 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2361 case X86_VENDOR_Centaur:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2362 if (cpi->cpi_family == 5)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2363 switch (cpi->cpi_model) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2364 case 4:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2365 brand = "Centaur C6";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2366 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2367 case 8:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2368 brand = "Centaur C2";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2369 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2370 case 9:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2371 brand = "Centaur C3";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2372 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2373 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2374 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2375 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2376 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2377 case X86_VENDOR_Rise:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2378 if (cpi->cpi_family == 5 &&
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2379 (cpi->cpi_model == 0 \|\| cpi->cpi_model == 2))
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2380 brand = "Rise mP6";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2381 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2382 case X86_VENDOR_SiS:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2383 if (cpi->cpi_family == 5 && cpi->cpi_model == 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2384 brand = "SiS 55x";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2385 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2386 case X86_VENDOR_TM:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2387 if (cpi->cpi_family == 5 && cpi->cpi_model == 4)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2388 brand = "Transmeta Crusoe TM3x00 or TM5x00";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2389 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2390 case X86_VENDOR_NSC:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2391 case X86_VENDOR_UMC:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2392 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2393 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2394 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2395 if (brand) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2396 (void) strcpy((char *)cpi->cpi_brandstr, brand);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2397 return;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2398 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2399
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2400 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2401 * If all else fails ...
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2402 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2403 (void) snprintf(cpi->cpi_brandstr, sizeof (cpi->cpi_brandstr),
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2404 "%s %d.%d.%d", cpi->cpi_vendorstr, cpi->cpi_family,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2405 cpi->cpi_model, cpi->cpi_step);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2406 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2407
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2408 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2409 * This routine is called just after kernel memory allocation
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2410 * becomes available on cpu0, and as part of mp_startup() on
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2411 * the other cpus.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2412 *
4606 ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2413 * Fixup the brand string, and collect any information from cpuid
14043 0291cd939b43 3506 Use "hypervisor" CPUID bit to detect hypervisor environment Yuri Pankov <yuri.pankov@nexenta.com> parents: 13905 diff changeset	2414 * that requires dynamically allocated storage to represent.
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2415 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2416 /ARGSUSED/
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2417 void
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2418 cpuid_pass3(cpu_t *cpu)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2419 {
4606 ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2420 int i, max, shft, level, size;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2421 struct cpuid_regs regs;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2422 struct cpuid_regs *cp;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2423 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2424
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2425 ASSERT(cpi->cpi_pass == 2);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2426
4606 ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2427 /*
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2428 * Function 4: Deterministic cache parameters
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2429 *
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2430 * Take this opportunity to detect the number of threads
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2431 * sharing the last level cache, and construct a corresponding
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2432 * cache id. The respective cpuid_info members are initialized
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2433 * to the default case of "no last level cache sharing".
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2434 */
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2435 cpi->cpi_ncpu_shr_last_cache = 1;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2436 cpi->cpi_last_lvl_cacheid = cpu->cpu_id;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2437
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2438 if (cpi->cpi_maxeax >= 4 && cpi->cpi_vendor == X86_VENDOR_Intel) {
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2439
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2440 /*
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2441 * Find the # of elements (size) returned by fn 4, and along
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2442 * the way detect last level cache sharing details.
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2443 */
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2444 bzero(&regs, sizeof (regs));
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2445 cp = &regs;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2446 for (i = 0, max = 0; i < CPI_FN4_ECX_MAX; i++) {
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2447 cp->cp_eax = 4;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2448 cp->cp_ecx = i;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2449
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2450 (void) __cpuid_insn(cp);
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2451
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2452 if (CPI_CACHE_TYPE(cp) == 0)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2453 break;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2454 level = CPI_CACHE_LVL(cp);
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2455 if (level > max) {
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2456 max = level;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2457 cpi->cpi_ncpu_shr_last_cache =
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2458 CPI_NTHR_SHR_CACHE(cp) + 1;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2459 }
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2460 }
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2461 cpi->cpi_std_4_size = size = i;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2462
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2463 /*
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2464 * Allocate the cpi_std_4 array. The first element
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2465 * references the regs for fn 4, %ecx == 0, which
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2466 * cpuid_pass2() stashed in cpi->cpi_std[4].
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2467 */
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2468 if (size > 0) {
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2469 cpi->cpi_std_4 =
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2470 kmem_alloc(size * sizeof (cp), KM_SLEEP);
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2471 cpi->cpi_std_4[0] = &cpi->cpi_std[4];
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2472
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2473 /*
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2474 * Allocate storage to hold the additional regs
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2475 * for function 4, %ecx == 1 .. cpi_std_4_size.
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2476 *
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2477 * The regs for fn 4, %ecx == 0 has already
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2478 * been allocated as indicated above.
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2479 */
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2480 for (i = 1; i < size; i++) {
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2481 cp = cpi->cpi_std_4[i] =
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2482 kmem_zalloc(sizeof (regs), KM_SLEEP);
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2483 cp->cp_eax = 4;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2484 cp->cp_ecx = i;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2485
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2486 (void) __cpuid_insn(cp);
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2487 }
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2488 }
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2489 /*
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2490 * Determine the number of bits needed to represent
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2491 * the number of CPUs sharing the last level cache.
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2492 *
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2493 * Shift off that number of bits from the APIC id to
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2494 * derive the cache id.
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2495 */
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2496 shft = 0;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2497 for (i = 1; i < cpi->cpi_ncpu_shr_last_cache; i <<= 1)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2498 shft++;
7282 5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	2499 cpi->cpi_last_lvl_cacheid = cpi->cpi_apicid >> shft;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2500 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2501
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2502 /*
4606 ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2503 * Now fixup the brand string
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2504 */
4606 ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2505 if ((cpi->cpi_xmaxeax & 0x80000000) == 0) {
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2506 fabricate_brandstr(cpi);
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2507 } else {
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2508
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2509 /*
4606 ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2510 * If we successfully extracted a brand string from the cpuid
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2511 * instruction, clean it up by removing leading spaces and
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2512 * similar junk.
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2513 */
4606 ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2514 if (cpi->cpi_brandstr[0]) {
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2515 size_t maxlen = sizeof (cpi->cpi_brandstr);
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2516 char src, dst;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2517
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2518 dst = src = (char *)cpi->cpi_brandstr;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2519 src[maxlen - 1] = '\0';
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2520 /*
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2521 * strip leading spaces
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2522 */
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2523 while (*src == ' ')
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2524 src++;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2525 /*
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2526 * Remove any 'Genuine' or "Authentic" prefixes
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2527 */
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2528 if (strncmp(src, "Genuine ", 8) == 0)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2529 src += 8;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2530 if (strncmp(src, "Authentic ", 10) == 0)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2531 src += 10;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2532
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2533 /*
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2534 * Now do an in-place copy.
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2535 * Map (R) to (r) and (TM) to (tm).
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2536 * The era of teletypes is long gone, and there's
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2537 * -really- no need to shout.
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2538 */
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2539 while (*src != '\0') {
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2540 if (src[0] == '(') {
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2541 if (strncmp(src + 1, "R)", 2) == 0) {
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2542 (void) strncpy(dst, "(r)", 3);
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2543 src += 3;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2544 dst += 3;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2545 continue;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2546 }
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2547 if (strncmp(src + 1, "TM)", 3) == 0) {
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2548 (void) strncpy(dst, "(tm)", 4);
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2549 src += 4;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2550 dst += 4;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2551 continue;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2552 }
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2553 }
4606 ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2554 dst++ = src++;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2555 }
4606 ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2556 *dst = '\0';
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2557
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2558 /*
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2559 * Finally, remove any trailing spaces
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2560 */
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2561 while (--dst > cpi->cpi_brandstr)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2562 if (*dst == ' ')
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2563 *dst = '\0';
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2564 else
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2565 break;
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2566 } else
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2567 fabricate_brandstr(cpi);
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2568 }
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2569 cpi->cpi_pass = 3;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2570 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2571
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2572 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2573 * This routine is called out of bind_hwcap() much later in the life
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2574 * of the kernel (post_startup()). The job of this routine is to resolve
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2575 * the hardware feature support and kernel support for those features into
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2576 * what we're actually going to tell applications via the aux vector.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2577 */
13905 b151bd260b71 3414 Need a new word of AT_SUN_HWCAP bits Robert Mustacchi <rm@joyent.com> parents: 13681 diff changeset	2578 void
b151bd260b71 3414 Need a new word of AT_SUN_HWCAP bits Robert Mustacchi <rm@joyent.com> parents: 13681 diff changeset	2579 cpuid_pass4(cpu_t cpu, uint_t hwcap_out)
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2580 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2581 struct cpuid_info *cpi;
13905 b151bd260b71 3414 Need a new word of AT_SUN_HWCAP bits Robert Mustacchi <rm@joyent.com> parents: 13681 diff changeset	2582 uint_t hwcap_flags = 0, hwcap_flags_2 = 0;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2583
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2584 if (cpu == NULL)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2585 cpu = CPU;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2586 cpi = cpu->cpu_m.mcpu_cpi;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2587
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2588 ASSERT(cpi->cpi_pass == 3);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2589
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2590 if (cpi->cpi_maxeax >= 1) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2591 uint32_t *edx = &cpi->cpi_support[STD_EDX_FEATURES];
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2592 uint32_t *ecx = &cpi->cpi_support[STD_ECX_FEATURES];
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2593
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2594 *edx = CPI_FEATURES_EDX(cpi);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2595 *ecx = CPI_FEATURES_ECX(cpi);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2596
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2597 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2598 * [these require explicit kernel support]
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2599 */
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	2600 if (!is_x86_feature(x86_featureset, X86FSET_SEP))
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2601 *edx &= ~CPUID_INTC_EDX_SEP;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2602
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	2603 if (!is_x86_feature(x86_featureset, X86FSET_SSE))
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2604 *edx &= ~(CPUID_INTC_EDX_FXSR\|CPUID_INTC_EDX_SSE);
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	2605 if (!is_x86_feature(x86_featureset, X86FSET_SSE2))
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2606 *edx &= ~CPUID_INTC_EDX_SSE2;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2607
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	2608 if (!is_x86_feature(x86_featureset, X86FSET_HTT))
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2609 *edx &= ~CPUID_INTC_EDX_HTT;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2610
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	2611 if (!is_x86_feature(x86_featureset, X86FSET_SSE3))
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2612 *ecx &= ~CPUID_INTC_ECX_SSE3;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2613
13655 0461a7e94e53 2412 Various CPU features aren't intel specific Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13651 diff changeset	2614 if (!is_x86_feature(x86_featureset, X86FSET_SSSE3))
0461a7e94e53 2412 Various CPU features aren't intel specific Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13651 diff changeset	2615 *ecx &= ~CPUID_INTC_ECX_SSSE3;
0461a7e94e53 2412 Various CPU features aren't intel specific Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13651 diff changeset	2616 if (!is_x86_feature(x86_featureset, X86FSET_SSE4_1))
0461a7e94e53 2412 Various CPU features aren't intel specific Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13651 diff changeset	2617 *ecx &= ~CPUID_INTC_ECX_SSE4_1;
0461a7e94e53 2412 Various CPU features aren't intel specific Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13651 diff changeset	2618 if (!is_x86_feature(x86_featureset, X86FSET_SSE4_2))
0461a7e94e53 2412 Various CPU features aren't intel specific Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13651 diff changeset	2619 *ecx &= ~CPUID_INTC_ECX_SSE4_2;
0461a7e94e53 2412 Various CPU features aren't intel specific Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13651 diff changeset	2620 if (!is_x86_feature(x86_featureset, X86FSET_AES))
0461a7e94e53 2412 Various CPU features aren't intel specific Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13651 diff changeset	2621 *ecx &= ~CPUID_INTC_ECX_AES;
0461a7e94e53 2412 Various CPU features aren't intel specific Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13651 diff changeset	2622 if (!is_x86_feature(x86_featureset, X86FSET_PCLMULQDQ))
0461a7e94e53 2412 Various CPU features aren't intel specific Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13651 diff changeset	2623 *ecx &= ~CPUID_INTC_ECX_PCLMULQDQ;
0461a7e94e53 2412 Various CPU features aren't intel specific Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13651 diff changeset	2624 if (!is_x86_feature(x86_featureset, X86FSET_XSAVE))
0461a7e94e53 2412 Various CPU features aren't intel specific Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13651 diff changeset	2625 *ecx &= ~(CPUID_INTC_ECX_XSAVE \|
0461a7e94e53 2412 Various CPU features aren't intel specific Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13651 diff changeset	2626 CPUID_INTC_ECX_OSXSAVE);
0461a7e94e53 2412 Various CPU features aren't intel specific Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13651 diff changeset	2627 if (!is_x86_feature(x86_featureset, X86FSET_AVX))
0461a7e94e53 2412 Various CPU features aren't intel specific Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13651 diff changeset	2628 *ecx &= ~CPUID_INTC_ECX_AVX;
13905 b151bd260b71 3414 Need a new word of AT_SUN_HWCAP bits Robert Mustacchi <rm@joyent.com> parents: 13681 diff changeset	2629 if (!is_x86_feature(x86_featureset, X86FSET_F16C))
b151bd260b71 3414 Need a new word of AT_SUN_HWCAP bits Robert Mustacchi <rm@joyent.com> parents: 13681 diff changeset	2630 *ecx &= ~CPUID_INTC_ECX_F16C;
5269 395a95dbfd17 6526262 cpuid ssse3 feature not noted on Intel Woodcrest/Conroe processors kk208521 parents: 5254 diff changeset	2631
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2632 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2633 * [no explicit support required beyond x87 fp context]
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2634 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2635 if (!fpu_exists)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2636 *edx &= ~(CPUID_INTC_EDX_FPU \| CPUID_INTC_EDX_MMX);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2637
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2638 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2639 * Now map the supported feature vector to things that we
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2640 * think userland will care about.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2641 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2642 if (*edx & CPUID_INTC_EDX_SEP)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2643 hwcap_flags \|= AV_386_SEP;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2644 if (*edx & CPUID_INTC_EDX_SSE)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2645 hwcap_flags \|= AV_386_FXSR \| AV_386_SSE;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2646 if (*edx & CPUID_INTC_EDX_SSE2)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2647 hwcap_flags \|= AV_386_SSE2;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2648 if (*ecx & CPUID_INTC_ECX_SSE3)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2649 hwcap_flags \|= AV_386_SSE3;
13655 0461a7e94e53 2412 Various CPU features aren't intel specific Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13651 diff changeset	2650 if (*ecx & CPUID_INTC_ECX_SSSE3)
0461a7e94e53 2412 Various CPU features aren't intel specific Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13651 diff changeset	2651 hwcap_flags \|= AV_386_SSSE3;
0461a7e94e53 2412 Various CPU features aren't intel specific Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13651 diff changeset	2652 if (*ecx & CPUID_INTC_ECX_SSE4_1)
0461a7e94e53 2412 Various CPU features aren't intel specific Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13651 diff changeset	2653 hwcap_flags \|= AV_386_SSE4_1;
0461a7e94e53 2412 Various CPU features aren't intel specific Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13651 diff changeset	2654 if (*ecx & CPUID_INTC_ECX_SSE4_2)
0461a7e94e53 2412 Various CPU features aren't intel specific Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13651 diff changeset	2655 hwcap_flags \|= AV_386_SSE4_2;
0461a7e94e53 2412 Various CPU features aren't intel specific Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13651 diff changeset	2656 if (*ecx & CPUID_INTC_ECX_MOVBE)
0461a7e94e53 2412 Various CPU features aren't intel specific Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13651 diff changeset	2657 hwcap_flags \|= AV_386_MOVBE;
0461a7e94e53 2412 Various CPU features aren't intel specific Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13651 diff changeset	2658 if (*ecx & CPUID_INTC_ECX_AES)
0461a7e94e53 2412 Various CPU features aren't intel specific Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13651 diff changeset	2659 hwcap_flags \|= AV_386_AES;
0461a7e94e53 2412 Various CPU features aren't intel specific Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13651 diff changeset	2660 if (*ecx & CPUID_INTC_ECX_PCLMULQDQ)
0461a7e94e53 2412 Various CPU features aren't intel specific Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13651 diff changeset	2661 hwcap_flags \|= AV_386_PCLMULQDQ;
0461a7e94e53 2412 Various CPU features aren't intel specific Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13651 diff changeset	2662 if ((*ecx & CPUID_INTC_ECX_XSAVE) &&
13675 a9ae30c28ee4 2413 %ymm* need to be preserved on way through PLT Robert Mustacchi <rm@joyent.com> parents: 13655 diff changeset	2663 (*ecx & CPUID_INTC_ECX_OSXSAVE)) {
13655 0461a7e94e53 2412 Various CPU features aren't intel specific Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13651 diff changeset	2664 hwcap_flags \|= AV_386_XSAVE;
13675 a9ae30c28ee4 2413 %ymm* need to be preserved on way through PLT Robert Mustacchi <rm@joyent.com> parents: 13655 diff changeset	2665
13905 b151bd260b71 3414 Need a new word of AT_SUN_HWCAP bits Robert Mustacchi <rm@joyent.com> parents: 13681 diff changeset	2666 if (*ecx & CPUID_INTC_ECX_AVX) {
13675 a9ae30c28ee4 2413 %ymm* need to be preserved on way through PLT Robert Mustacchi <rm@joyent.com> parents: 13655 diff changeset	2667 hwcap_flags \|= AV_386_AVX;
13905 b151bd260b71 3414 Need a new word of AT_SUN_HWCAP bits Robert Mustacchi <rm@joyent.com> parents: 13681 diff changeset	2668 if (*ecx & CPUID_INTC_ECX_F16C)
b151bd260b71 3414 Need a new word of AT_SUN_HWCAP bits Robert Mustacchi <rm@joyent.com> parents: 13681 diff changeset	2669 hwcap_flags_2 \|= AV_386_2_F16C;
b151bd260b71 3414 Need a new word of AT_SUN_HWCAP bits Robert Mustacchi <rm@joyent.com> parents: 13681 diff changeset	2670 }
13675 a9ae30c28ee4 2413 %ymm* need to be preserved on way through PLT Robert Mustacchi <rm@joyent.com> parents: 13655 diff changeset	2671 }
13425 8640246a3548 1347 isainfo should indicate presence of vmx/svm support Bryan Cantrill <bryan@joyent.com> parents: 13148 diff changeset	2672 if (*ecx & CPUID_INTC_ECX_VMX)
8640246a3548 1347 isainfo should indicate presence of vmx/svm support Bryan Cantrill <bryan@joyent.com> parents: 13148 diff changeset	2673 hwcap_flags \|= AV_386_VMX;
4628 f90cf8fd4710 6525798 Need Hardware Capabilities support for AMD Family 10h/sse4a processor kk208521 parents: 4606 diff changeset	2674 if (*ecx & CPUID_INTC_ECX_POPCNT)
f90cf8fd4710 6525798 Need Hardware Capabilities support for AMD Family 10h/sse4a processor kk208521 parents: 4606 diff changeset	2675 hwcap_flags \|= AV_386_POPCNT;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2676 if (*edx & CPUID_INTC_EDX_FPU)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2677 hwcap_flags \|= AV_386_FPU;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2678 if (*edx & CPUID_INTC_EDX_MMX)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2679 hwcap_flags \|= AV_386_MMX;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2680
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2681 if (*edx & CPUID_INTC_EDX_TSC)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2682 hwcap_flags \|= AV_386_TSC;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2683 if (*edx & CPUID_INTC_EDX_CX8)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2684 hwcap_flags \|= AV_386_CX8;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2685 if (*edx & CPUID_INTC_EDX_CMOV)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2686 hwcap_flags \|= AV_386_CMOV;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2687 if (*ecx & CPUID_INTC_ECX_CX16)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2688 hwcap_flags \|= AV_386_CX16;
13905 b151bd260b71 3414 Need a new word of AT_SUN_HWCAP bits Robert Mustacchi <rm@joyent.com> parents: 13681 diff changeset	2689
b151bd260b71 3414 Need a new word of AT_SUN_HWCAP bits Robert Mustacchi <rm@joyent.com> parents: 13681 diff changeset	2690 if (*ecx & CPUID_INTC_ECX_RDRAND)
b151bd260b71 3414 Need a new word of AT_SUN_HWCAP bits Robert Mustacchi <rm@joyent.com> parents: 13681 diff changeset	2691 hwcap_flags_2 \|= AV_386_2_RDRAND;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2692 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2693
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2694 if (cpi->cpi_xmaxeax < 0x80000001)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2695 goto pass4_done;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2696
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2697 switch (cpi->cpi_vendor) {
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2698 struct cpuid_regs cp;
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2699 uint32_t edx, ecx;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2700
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2701 case X86_VENDOR_Intel:
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2702 /*
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2703 * Seems like Intel duplicated what we necessary
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2704 * here to make the initial crop of 64-bit OS's work.
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2705 * Hopefully, those are the only "extended" bits
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2706 * they'll add.
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2707 */
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2708 /FALLTHROUGH/
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2709
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2710 case X86_VENDOR_AMD:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2711 edx = &cpi->cpi_support[AMD_EDX_FEATURES];
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2712 ecx = &cpi->cpi_support[AMD_ECX_FEATURES];
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2713
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2714 *edx = CPI_FEATURES_XTD_EDX(cpi);
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2715 *ecx = CPI_FEATURES_XTD_ECX(cpi);
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2716
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2717 /*
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2718 * [these features require explicit kernel support]
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2719 */
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2720 switch (cpi->cpi_vendor) {
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2721 case X86_VENDOR_Intel:
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	2722 if (!is_x86_feature(x86_featureset, X86FSET_TSCP))
6657 a55676c65ac7 6628773 Need to support rdtscp for Intel sudheer parents: 6642 diff changeset	2723 *edx &= ~CPUID_AMD_EDX_TSCP;
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2724 break;
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2725
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2726 case X86_VENDOR_AMD:
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	2727 if (!is_x86_feature(x86_featureset, X86FSET_TSCP))
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2728 *edx &= ~CPUID_AMD_EDX_TSCP;
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	2729 if (!is_x86_feature(x86_featureset, X86FSET_SSE4A))
4628 f90cf8fd4710 6525798 Need Hardware Capabilities support for AMD Family 10h/sse4a processor kk208521 parents: 4606 diff changeset	2730 *ecx &= ~CPUID_AMD_ECX_SSE4A;
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2731 break;
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2732
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2733 default:
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2734 break;
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2735 }
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2736
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2737 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2738 * [no explicit support required beyond
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2739 * x87 fp context and exception handlers]
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2740 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2741 if (!fpu_exists)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2742 *edx &= ~(CPUID_AMD_EDX_MMXamd \|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2743 CPUID_AMD_EDX_3DNow \| CPUID_AMD_EDX_3DNowx);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2744
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	2745 if (!is_x86_feature(x86_featureset, X86FSET_NX))
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2746 *edx &= ~CPUID_AMD_EDX_NX;
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2747 #if !defined(__amd64)
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2748 *edx &= ~CPUID_AMD_EDX_LM;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2749 #endif
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2750 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2751 * Now map the supported feature vector to
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2752 * things that we think userland will care about.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2753 */
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2754 #if defined(__amd64)
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2755 if (*edx & CPUID_AMD_EDX_SYSC)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2756 hwcap_flags \|= AV_386_AMD_SYSC;
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2757 #endif
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2758 if (*edx & CPUID_AMD_EDX_MMXamd)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2759 hwcap_flags \|= AV_386_AMD_MMX;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2760 if (*edx & CPUID_AMD_EDX_3DNow)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2761 hwcap_flags \|= AV_386_AMD_3DNow;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2762 if (*edx & CPUID_AMD_EDX_3DNowx)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2763 hwcap_flags \|= AV_386_AMD_3DNowx;
13425 8640246a3548 1347 isainfo should indicate presence of vmx/svm support Bryan Cantrill <bryan@joyent.com> parents: 13148 diff changeset	2764 if (*ecx & CPUID_AMD_ECX_SVM)
8640246a3548 1347 isainfo should indicate presence of vmx/svm support Bryan Cantrill <bryan@joyent.com> parents: 13148 diff changeset	2765 hwcap_flags \|= AV_386_AMD_SVM;
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2766
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2767 switch (cpi->cpi_vendor) {
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2768 case X86_VENDOR_AMD:
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2769 if (*edx & CPUID_AMD_EDX_TSCP)
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2770 hwcap_flags \|= AV_386_TSCP;
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2771 if (*ecx & CPUID_AMD_ECX_AHF64)
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2772 hwcap_flags \|= AV_386_AHF;
4628 f90cf8fd4710 6525798 Need Hardware Capabilities support for AMD Family 10h/sse4a processor kk208521 parents: 4606 diff changeset	2773 if (*ecx & CPUID_AMD_ECX_SSE4A)
f90cf8fd4710 6525798 Need Hardware Capabilities support for AMD Family 10h/sse4a processor kk208521 parents: 4606 diff changeset	2774 hwcap_flags \|= AV_386_AMD_SSE4A;
f90cf8fd4710 6525798 Need Hardware Capabilities support for AMD Family 10h/sse4a processor kk208521 parents: 4606 diff changeset	2775 if (*ecx & CPUID_AMD_ECX_LZCNT)
f90cf8fd4710 6525798 Need Hardware Capabilities support for AMD Family 10h/sse4a processor kk208521 parents: 4606 diff changeset	2776 hwcap_flags \|= AV_386_AMD_LZCNT;
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2777 break;
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2778
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2779 case X86_VENDOR_Intel:
6657 a55676c65ac7 6628773 Need to support rdtscp for Intel sudheer parents: 6642 diff changeset	2780 if (*edx & CPUID_AMD_EDX_TSCP)
a55676c65ac7 6628773 Need to support rdtscp for Intel sudheer parents: 6642 diff changeset	2781 hwcap_flags \|= AV_386_TSCP;
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2782 /*
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2783 * Aarrgh.
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2784 * Intel uses a different bit in the same word.
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2785 */
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2786 if (*ecx & CPUID_INTC_ECX_AHF64)
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2787 hwcap_flags \|= AV_386_AHF;
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2788 break;
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2789
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2790 default:
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2791 break;
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2792 }
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2793 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2794
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2795 case X86_VENDOR_TM:
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2796 cp.cp_eax = 0x80860001;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2797 (void) __cpuid_insn(&cp);
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2798 cpi->cpi_support[TM_EDX_FEATURES] = cp.cp_edx;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2799 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2800
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2801 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2802 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2803 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2804
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2805 pass4_done:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2806 cpi->cpi_pass = 4;
13905 b151bd260b71 3414 Need a new word of AT_SUN_HWCAP bits Robert Mustacchi <rm@joyent.com> parents: 13681 diff changeset	2807 if (hwcap_out != NULL) {
b151bd260b71 3414 Need a new word of AT_SUN_HWCAP bits Robert Mustacchi <rm@joyent.com> parents: 13681 diff changeset	2808 hwcap_out[0] = hwcap_flags;
b151bd260b71 3414 Need a new word of AT_SUN_HWCAP bits Robert Mustacchi <rm@joyent.com> parents: 13681 diff changeset	2809 hwcap_out[1] = hwcap_flags_2;
b151bd260b71 3414 Need a new word of AT_SUN_HWCAP bits Robert Mustacchi <rm@joyent.com> parents: 13681 diff changeset	2810 }
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2811 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2812
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2813
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2814 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2815 * Simulate the cpuid instruction using the data we previously
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2816 * captured about this CPU. We try our best to return the truth
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2817 * about the hardware, independently of kernel support.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2818 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2819 uint32_t
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2820 cpuid_insn(cpu_t cpu, struct cpuid_regs cp)
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2821 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2822 struct cpuid_info *cpi;
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2823 struct cpuid_regs *xcp;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2824
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2825 if (cpu == NULL)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2826 cpu = CPU;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2827 cpi = cpu->cpu_m.mcpu_cpi;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2828
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2829 ASSERT(cpuid_checkpass(cpu, 3));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2830
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2831 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2832 * CPUID data is cached in two separate places: cpi_std for standard
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2833 * CPUID functions, and cpi_extd for extended CPUID functions.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2834 */
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2835 if (cp->cp_eax <= cpi->cpi_maxeax && cp->cp_eax < NMAX_CPI_STD)
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2836 xcp = &cpi->cpi_std[cp->cp_eax];
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2837 else if (cp->cp_eax >= 0x80000000 && cp->cp_eax <= cpi->cpi_xmaxeax &&
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2838 cp->cp_eax < 0x80000000 + NMAX_CPI_EXTD)
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2839 xcp = &cpi->cpi_extd[cp->cp_eax - 0x80000000];
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2840 else
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2841 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2842 * The caller is asking for data from an input parameter which
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2843 * the kernel has not cached. In this case we go fetch from
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2844 * the hardware and return the data directly to the user.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2845 */
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2846 return (__cpuid_insn(cp));
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2847
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2848 cp->cp_eax = xcp->cp_eax;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2849 cp->cp_ebx = xcp->cp_ebx;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2850 cp->cp_ecx = xcp->cp_ecx;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2851 cp->cp_edx = xcp->cp_edx;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2852 return (cp->cp_eax);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2853 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2854
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2855 int
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2856 cpuid_checkpass(cpu_t *cpu, int pass)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2857 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2858 return (cpu != NULL && cpu->cpu_m.mcpu_cpi != NULL &&
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2859 cpu->cpu_m.mcpu_cpi->cpi_pass >= pass);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2860 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2861
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2862 int
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2863 cpuid_getbrandstr(cpu_t cpu, char s, size_t n)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2864 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2865 ASSERT(cpuid_checkpass(cpu, 3));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2866
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2867 return (snprintf(s, n, "%s", cpu->cpu_m.mcpu_cpi->cpi_brandstr));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2868 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2869
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2870 int
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2871 cpuid_is_cmt(cpu_t *cpu)
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2872 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2873 if (cpu == NULL)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2874 cpu = CPU;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2875
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2876 ASSERT(cpuid_checkpass(cpu, 1));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2877
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2878 return (cpu->cpu_m.mcpu_cpi->cpi_chipid >= 0);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2879 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2880
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2881 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2882 * AMD and Intel both implement the 64-bit variant of the syscall
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2883 * instruction (syscallq), so if there's -any- support for syscall,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2884 * cpuid currently says "yes, we support this".
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2885 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2886 * However, Intel decided to -not- implement the 32-bit variant of the
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2887 * syscall instruction, so we provide a predicate to allow our caller
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2888 * to test that subtlety here.
5084 7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	2889 *
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	2890 * XXPV Currently, 32-bit syscall instructions don't work via the hypervisor,
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	2891 * even in the case where the hardware would in fact support it.
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2892 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2893 /ARGSUSED/
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2894 int
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2895 cpuid_syscall32_insn(cpu_t *cpu)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2896 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2897 ASSERT(cpuid_checkpass((cpu == NULL ? CPU : cpu), 1));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2898
5084 7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	2899 #if !defined(__xpv)
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2900 if (cpu == NULL)
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2901 cpu = CPU;
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2902
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2903 /CSTYLED/
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2904 {
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2905 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2906
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2907 if (cpi->cpi_vendor == X86_VENDOR_AMD &&
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2908 cpi->cpi_xmaxeax >= 0x80000001 &&
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2909 (CPI_FEATURES_XTD_EDX(cpi) & CPUID_AMD_EDX_SYSC))
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2910 return (1);
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	2911 }
5084 7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	2912 #endif
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2913 return (0);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2914 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2915
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2916 int
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2917 cpuid_getidstr(cpu_t cpu, char s, size_t n)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2918 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2919 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2920
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2921 static const char fmt[] =
3779 f34a44686f8b 6532527 psrinfo output should show "EAX Page 1" hex value to identify processors dmick parents: 3446 diff changeset	2922 "x86 (%s %X family %d model %d step %d clock %d MHz)";
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2923 static const char fmt_ht[] =
3779 f34a44686f8b 6532527 psrinfo output should show "EAX Page 1" hex value to identify processors dmick parents: 3446 diff changeset	2924 "x86 (chipid 0x%x %s %X family %d model %d step %d clock %d MHz)";
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2925
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2926 ASSERT(cpuid_checkpass(cpu, 1));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2927
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2928 if (cpuid_is_cmt(cpu))
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2929 return (snprintf(s, n, fmt_ht, cpi->cpi_chipid,
3779 f34a44686f8b 6532527 psrinfo output should show "EAX Page 1" hex value to identify processors dmick parents: 3446 diff changeset	2930 cpi->cpi_vendorstr, cpi->cpi_std[1].cp_eax,
f34a44686f8b 6532527 psrinfo output should show "EAX Page 1" hex value to identify processors dmick parents: 3446 diff changeset	2931 cpi->cpi_family, cpi->cpi_model,
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2932 cpi->cpi_step, cpu->cpu_type_info.pi_clock));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2933 return (snprintf(s, n, fmt,
3779 f34a44686f8b 6532527 psrinfo output should show "EAX Page 1" hex value to identify processors dmick parents: 3446 diff changeset	2934 cpi->cpi_vendorstr, cpi->cpi_std[1].cp_eax,
f34a44686f8b 6532527 psrinfo output should show "EAX Page 1" hex value to identify processors dmick parents: 3446 diff changeset	2935 cpi->cpi_family, cpi->cpi_model,
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2936 cpi->cpi_step, cpu->cpu_type_info.pi_clock));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2937 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2938
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2939 const char *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2940 cpuid_getvendorstr(cpu_t *cpu)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2941 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2942 ASSERT(cpuid_checkpass(cpu, 1));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2943 return ((const char *)cpu->cpu_m.mcpu_cpi->cpi_vendorstr);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2944 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2945
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2946 uint_t
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2947 cpuid_getvendor(cpu_t *cpu)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2948 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2949 ASSERT(cpuid_checkpass(cpu, 1));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2950 return (cpu->cpu_m.mcpu_cpi->cpi_vendor);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2951 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2952
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2953 uint_t
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2954 cpuid_getfamily(cpu_t *cpu)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2955 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2956 ASSERT(cpuid_checkpass(cpu, 1));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2957 return (cpu->cpu_m.mcpu_cpi->cpi_family);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2958 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2959
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2960 uint_t
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2961 cpuid_getmodel(cpu_t *cpu)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2962 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2963 ASSERT(cpuid_checkpass(cpu, 1));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2964 return (cpu->cpu_m.mcpu_cpi->cpi_model);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2965 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2966
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2967 uint_t
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2968 cpuid_get_ncpu_per_chip(cpu_t *cpu)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2969 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2970 ASSERT(cpuid_checkpass(cpu, 1));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2971 return (cpu->cpu_m.mcpu_cpi->cpi_ncpu_per_chip);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2972 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2973
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2974 uint_t
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2975 cpuid_get_ncore_per_chip(cpu_t *cpu)
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2976 {
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2977 ASSERT(cpuid_checkpass(cpu, 1));
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2978 return (cpu->cpu_m.mcpu_cpi->cpi_ncore_per_chip);
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2979 }
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2980
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	2981 uint_t
4606 ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2982 cpuid_get_ncpu_sharing_last_cache(cpu_t *cpu)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2983 {
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2984 ASSERT(cpuid_checkpass(cpu, 2));
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2985 return (cpu->cpu_m.mcpu_cpi->cpi_ncpu_shr_last_cache);
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2986 }
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2987
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2988 id_t
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2989 cpuid_get_last_lvl_cacheid(cpu_t *cpu)
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2990 {
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2991 ASSERT(cpuid_checkpass(cpu, 2));
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2992 return (cpu->cpu_m.mcpu_cpi->cpi_last_lvl_cacheid);
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2993 }
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2994
ffcd05844ec5 6495401 cpuid based cache hierarchy awareness esaxe parents: 4581 diff changeset	2995 uint_t
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2996 cpuid_getstep(cpu_t *cpu)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2997 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2998 ASSERT(cpuid_checkpass(cpu, 1));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	2999 return (cpu->cpu_m.mcpu_cpi->cpi_step);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3000 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3001
4581 b6104e41b06c PSARC/2007/349 Intel Microcode Update Support sherrym parents: 4481 diff changeset	3002 uint_t
b6104e41b06c PSARC/2007/349 Intel Microcode Update Support sherrym parents: 4481 diff changeset	3003 cpuid_getsig(struct cpu *cpu)
b6104e41b06c PSARC/2007/349 Intel Microcode Update Support sherrym parents: 4481 diff changeset	3004 {
b6104e41b06c PSARC/2007/349 Intel Microcode Update Support sherrym parents: 4481 diff changeset	3005 ASSERT(cpuid_checkpass(cpu, 1));
b6104e41b06c PSARC/2007/349 Intel Microcode Update Support sherrym parents: 4481 diff changeset	3006 return (cpu->cpu_m.mcpu_cpi->cpi_std[1].cp_eax);
b6104e41b06c PSARC/2007/349 Intel Microcode Update Support sherrym parents: 4481 diff changeset	3007 }
b6104e41b06c PSARC/2007/349 Intel Microcode Update Support sherrym parents: 4481 diff changeset	3008
2869 324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	3009 uint32_t
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	3010 cpuid_getchiprev(struct cpu *cpu)
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	3011 {
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	3012 ASSERT(cpuid_checkpass(cpu, 1));
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	3013 return (cpu->cpu_m.mcpu_cpi->cpi_chiprev);
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	3014 }
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	3015
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	3016 const char *
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	3017 cpuid_getchiprevstr(struct cpu *cpu)
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	3018 {
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	3019 ASSERT(cpuid_checkpass(cpu, 1));
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	3020 return (cpu->cpu_m.mcpu_cpi->cpi_chiprevstr);
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	3021 }
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	3022
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	3023 uint32_t
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	3024 cpuid_getsockettype(struct cpu *cpu)
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	3025 {
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	3026 ASSERT(cpuid_checkpass(cpu, 1));
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	3027 return (cpu->cpu_m.mcpu_cpi->cpi_socket);
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	3028 }
324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	3029
9482 42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	3030 const char *
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	3031 cpuid_getsocketstr(cpu_t *cpu)
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	3032 {
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	3033 static const char *socketstr = NULL;
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	3034 struct cpuid_info *cpi;
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	3035
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	3036 ASSERT(cpuid_checkpass(cpu, 1));
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	3037 cpi = cpu->cpu_m.mcpu_cpi;
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	3038
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	3039 /* Assume that socket types are the same across the system */
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	3040 if (socketstr == NULL)
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	3041 socketstr = _cpuid_sktstr(cpi->cpi_vendor, cpi->cpi_family,
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	3042 cpi->cpi_model, cpi->cpi_step);
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	3043
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	3044
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	3045 return (socketstr);
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	3046 }
42f3d60af7ca 6770233 New model ID for Istanbul processor Kuriakose Kuruvilla <Kuriakose.Kuruvilla@Sun.COM> parents: 9370 diff changeset	3047
3434 5142e1d7d0bc 6461311 multi-level CMT scheduling optimizations esaxe parents: 2869 diff changeset	3048 int
5142e1d7d0bc 6461311 multi-level CMT scheduling optimizations esaxe parents: 2869 diff changeset	3049 cpuid_get_chipid(cpu_t *cpu)
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3050 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3051 ASSERT(cpuid_checkpass(cpu, 1));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3052
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	3053 if (cpuid_is_cmt(cpu))
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3054 return (cpu->cpu_m.mcpu_cpi->cpi_chipid);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3055 return (cpu->cpu_id);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3056 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3057
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	3058 id_t
3434 5142e1d7d0bc 6461311 multi-level CMT scheduling optimizations esaxe parents: 2869 diff changeset	3059 cpuid_get_coreid(cpu_t *cpu)
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	3060 {
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	3061 ASSERT(cpuid_checkpass(cpu, 1));
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	3062 return (cpu->cpu_m.mcpu_cpi->cpi_coreid);
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	3063 }
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	3064
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3065 int
5870 2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	3066 cpuid_get_pkgcoreid(cpu_t *cpu)
2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	3067 {
2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	3068 ASSERT(cpuid_checkpass(cpu, 1));
2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	3069 return (cpu->cpu_m.mcpu_cpi->cpi_pkgcoreid);
2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	3070 }
2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	3071
2513339ac53a 6642169 cpu.generic panic during install of snv_76 and later builds gavinm parents: 5741 diff changeset	3072 int
3434 5142e1d7d0bc 6461311 multi-level CMT scheduling optimizations esaxe parents: 2869 diff changeset	3073 cpuid_get_clogid(cpu_t *cpu)
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3074 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3075 ASSERT(cpuid_checkpass(cpu, 1));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3076 return (cpu->cpu_m.mcpu_cpi->cpi_clogid);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3077 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3078
11389 dd00b884e84f 6764832 Provide user-level processor groups observability Alexander Kolbasov <Alexander.Kolbasov@Sun.COM> parents: 11013 diff changeset	3079 int
dd00b884e84f 6764832 Provide user-level processor groups observability Alexander Kolbasov <Alexander.Kolbasov@Sun.COM> parents: 11013 diff changeset	3080 cpuid_get_cacheid(cpu_t *cpu)
dd00b884e84f 6764832 Provide user-level processor groups observability Alexander Kolbasov <Alexander.Kolbasov@Sun.COM> parents: 11013 diff changeset	3081 {
dd00b884e84f 6764832 Provide user-level processor groups observability Alexander Kolbasov <Alexander.Kolbasov@Sun.COM> parents: 11013 diff changeset	3082 ASSERT(cpuid_checkpass(cpu, 1));
dd00b884e84f 6764832 Provide user-level processor groups observability Alexander Kolbasov <Alexander.Kolbasov@Sun.COM> parents: 11013 diff changeset	3083 return (cpu->cpu_m.mcpu_cpi->cpi_last_lvl_cacheid);
dd00b884e84f 6764832 Provide user-level processor groups observability Alexander Kolbasov <Alexander.Kolbasov@Sun.COM> parents: 11013 diff changeset	3084 }
dd00b884e84f 6764832 Provide user-level processor groups observability Alexander Kolbasov <Alexander.Kolbasov@Sun.COM> parents: 11013 diff changeset	3085
10947 2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	3086 uint_t
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	3087 cpuid_get_procnodeid(cpu_t *cpu)
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	3088 {
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	3089 ASSERT(cpuid_checkpass(cpu, 1));
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	3090 return (cpu->cpu_m.mcpu_cpi->cpi_procnodeid);
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	3091 }
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	3092
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	3093 uint_t
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	3094 cpuid_get_procnodes_per_pkg(cpu_t *cpu)
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	3095 {
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	3096 ASSERT(cpuid_checkpass(cpu, 1));
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	3097 return (cpu->cpu_m.mcpu_cpi->cpi_procnodes_per_pkg);
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	3098 }
2ecbb0a4d189 6843035 Need support for Magny-Cours processors Srihari Venkatesan <Srihari.Venkatesan@Sun.COM> parents: 10175 diff changeset	3099
13681 73253247f9e5 2650 AMD family 0x15 PG support Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13675 diff changeset	3100 uint_t
73253247f9e5 2650 AMD family 0x15 PG support Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13675 diff changeset	3101 cpuid_get_compunitid(cpu_t *cpu)
73253247f9e5 2650 AMD family 0x15 PG support Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13675 diff changeset	3102 {
73253247f9e5 2650 AMD family 0x15 PG support Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13675 diff changeset	3103 ASSERT(cpuid_checkpass(cpu, 1));
73253247f9e5 2650 AMD family 0x15 PG support Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13675 diff changeset	3104 return (cpu->cpu_m.mcpu_cpi->cpi_compunitid);
73253247f9e5 2650 AMD family 0x15 PG support Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13675 diff changeset	3105 }
73253247f9e5 2650 AMD family 0x15 PG support Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13675 diff changeset	3106
73253247f9e5 2650 AMD family 0x15 PG support Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13675 diff changeset	3107 uint_t
73253247f9e5 2650 AMD family 0x15 PG support Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13675 diff changeset	3108 cpuid_get_cores_per_compunit(cpu_t *cpu)
73253247f9e5 2650 AMD family 0x15 PG support Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13675 diff changeset	3109 {
73253247f9e5 2650 AMD family 0x15 PG support Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13675 diff changeset	3110 ASSERT(cpuid_checkpass(cpu, 1));
73253247f9e5 2650 AMD family 0x15 PG support Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13675 diff changeset	3111 return (cpu->cpu_m.mcpu_cpi->cpi_cores_per_compunit);
73253247f9e5 2650 AMD family 0x15 PG support Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13675 diff changeset	3112 }
73253247f9e5 2650 AMD family 0x15 PG support Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13675 diff changeset	3113
10080 29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	3114 /ARGSUSED/
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	3115 int
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	3116 cpuid_have_cr8access(cpu_t *cpu)
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	3117 {
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	3118 #if defined(__amd64)
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	3119 return (1);
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	3120 #else
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	3121 struct cpuid_info *cpi;
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	3122
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	3123 ASSERT(cpu != NULL);
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	3124 cpi = cpu->cpu_m.mcpu_cpi;
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	3125 if (cpi->cpi_vendor == X86_VENDOR_AMD && cpi->cpi_maxeax >= 1 &&
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	3126 (CPI_FEATURES_XTD_ECX(cpi) & CPUID_AMD_ECX_CR8D) != 0)
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	3127 return (1);
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	3128 return (0);
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	3129 #endif
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	3130 }
29a4a1bb9f3f 6848982 32 bit kernel should use %cr8 to access the TPR when possible Joe Bonasera <Joe.Bonasera@sun.com> parents: 9652 diff changeset	3131
9652 6b40e106879c 6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot Michael Corcoran <Michael.Corcoran@Sun.COM> parents: 9482 diff changeset	3132 uint32_t
6b40e106879c 6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot Michael Corcoran <Michael.Corcoran@Sun.COM> parents: 9482 diff changeset	3133 cpuid_get_apicid(cpu_t *cpu)
6b40e106879c 6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot Michael Corcoran <Michael.Corcoran@Sun.COM> parents: 9482 diff changeset	3134 {
6b40e106879c 6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot Michael Corcoran <Michael.Corcoran@Sun.COM> parents: 9482 diff changeset	3135 ASSERT(cpuid_checkpass(cpu, 1));
6b40e106879c 6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot Michael Corcoran <Michael.Corcoran@Sun.COM> parents: 9482 diff changeset	3136 if (cpu->cpu_m.mcpu_cpi->cpi_maxeax < 1) {
6b40e106879c 6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot Michael Corcoran <Michael.Corcoran@Sun.COM> parents: 9482 diff changeset	3137 return (UINT32_MAX);
6b40e106879c 6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot Michael Corcoran <Michael.Corcoran@Sun.COM> parents: 9482 diff changeset	3138 } else {
6b40e106879c 6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot Michael Corcoran <Michael.Corcoran@Sun.COM> parents: 9482 diff changeset	3139 return (cpu->cpu_m.mcpu_cpi->cpi_apicid);
6b40e106879c 6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot Michael Corcoran <Michael.Corcoran@Sun.COM> parents: 9482 diff changeset	3140 }
6b40e106879c 6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot Michael Corcoran <Michael.Corcoran@Sun.COM> parents: 9482 diff changeset	3141 }
6b40e106879c 6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot Michael Corcoran <Michael.Corcoran@Sun.COM> parents: 9482 diff changeset	3142
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3143 void
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3144 cpuid_get_addrsize(cpu_t cpu, uint_t pabits, uint_t *vabits)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3145 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3146 struct cpuid_info *cpi;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3147
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3148 if (cpu == NULL)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3149 cpu = CPU;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3150 cpi = cpu->cpu_m.mcpu_cpi;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3151
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3152 ASSERT(cpuid_checkpass(cpu, 1));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3153
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3154 if (pabits)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3155 *pabits = cpi->cpi_pabits;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3156 if (vabits)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3157 *vabits = cpi->cpi_vabits;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3158 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3159
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3160 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3161 * Returns the number of data TLB entries for a corresponding
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3162 * pagesize. If it can't be computed, or isn't known, the
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3163 * routine returns zero. If you ask about an architecturally
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3164 * impossible pagesize, the routine will panic (so that the
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3165 * hat implementor knows that things are inconsistent.)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3166 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3167 uint_t
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3168 cpuid_get_dtlb_nent(cpu_t *cpu, size_t pagesize)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3169 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3170 struct cpuid_info *cpi;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3171 uint_t dtlb_nent = 0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3172
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3173 if (cpu == NULL)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3174 cpu = CPU;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3175 cpi = cpu->cpu_m.mcpu_cpi;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3176
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3177 ASSERT(cpuid_checkpass(cpu, 1));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3178
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3179 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3180 * Check the L2 TLB info
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3181 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3182 if (cpi->cpi_xmaxeax >= 0x80000006) {
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	3183 struct cpuid_regs *cp = &cpi->cpi_extd[6];
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3184
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3185 switch (pagesize) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3186
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3187 case 4 * 1024:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3188 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3189 * All zero in the top 16 bits of the register
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3190 * indicates a unified TLB. Size is in low 16 bits.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3191 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3192 if ((cp->cp_ebx & 0xffff0000) == 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3193 dtlb_nent = cp->cp_ebx & 0x0000ffff;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3194 else
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3195 dtlb_nent = BITX(cp->cp_ebx, 27, 16);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3196 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3197
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3198 case 2 * 1024 * 1024:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3199 if ((cp->cp_eax & 0xffff0000) == 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3200 dtlb_nent = cp->cp_eax & 0x0000ffff;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3201 else
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3202 dtlb_nent = BITX(cp->cp_eax, 27, 16);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3203 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3204
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3205 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3206 panic("unknown L2 pagesize");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3207 /NOTREACHED/
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3208 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3209 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3210
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3211 if (dtlb_nent != 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3212 return (dtlb_nent);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3213
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3214 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3215 * No L2 TLB support for this size, try L1.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3216 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3217 if (cpi->cpi_xmaxeax >= 0x80000005) {
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	3218 struct cpuid_regs *cp = &cpi->cpi_extd[5];
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3219
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3220 switch (pagesize) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3221 case 4 * 1024:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3222 dtlb_nent = BITX(cp->cp_ebx, 23, 16);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3223 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3224 case 2 * 1024 * 1024:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3225 dtlb_nent = BITX(cp->cp_eax, 23, 16);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3226 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3227 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3228 panic("unknown L1 d-TLB pagesize");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3229 /NOTREACHED/
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3230 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3231 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3232
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3233 return (dtlb_nent);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3234 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3235
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3236 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3237 * Return 0 if the erratum is not present or not applicable, positive
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3238 * if it is, and negative if the status of the erratum is unknown.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3239 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3240 * See "Revision Guide for AMD Athlon(tm) 64 and AMD Opteron(tm)
359 a88cb999e7ec 6288246 amd64 kernel needs to detect AMD Opteron erratum 131 kucharsk parents: 0 diff changeset	3241 * Processors" #25759, Rev 3.57, August 2005
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3242 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3243 int
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3244 cpuid_opteron_erratum(cpu_t *cpu, uint_t erratum)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3245 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3246 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	3247 uint_t eax;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3248
2584 c8f937287646 6462189 cpuid_opteron_erratum does not bail out on non-AMD64 AMD CPUs sethg parents: 2519 diff changeset	3249 /*
c8f937287646 6462189 cpuid_opteron_erratum does not bail out on non-AMD64 AMD CPUs sethg parents: 2519 diff changeset	3250 * Bail out if this CPU isn't an AMD CPU, or if it's
c8f937287646 6462189 cpuid_opteron_erratum does not bail out on non-AMD64 AMD CPUs sethg parents: 2519 diff changeset	3251 * a legacy (32-bit) AMD CPU.
c8f937287646 6462189 cpuid_opteron_erratum does not bail out on non-AMD64 AMD CPUs sethg parents: 2519 diff changeset	3252 */
c8f937287646 6462189 cpuid_opteron_erratum does not bail out on non-AMD64 AMD CPUs sethg parents: 2519 diff changeset	3253 if (cpi->cpi_vendor != X86_VENDOR_AMD \|\|
4265 6be078c4d3b4 6555108 workarounds being applied for errata not present in greyhound processors kchow parents: 3779 diff changeset	3254 cpi->cpi_family == 4 \|\| cpi->cpi_family == 5 \|\|
6be078c4d3b4 6555108 workarounds being applied for errata not present in greyhound processors kchow parents: 3779 diff changeset	3255 cpi->cpi_family == 6)
2869 324151eecd58 PSARC 2006/564 FMA for Athlon 64 and Opteron Rev F/G Processors gavinm parents: 2584 diff changeset	3256
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3257 return (0);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3258
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3259 eax = cpi->cpi_std[1].cp_eax;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3260
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3261 #define SH_B0(eax) (eax == 0xf40 \|\| eax == 0xf50)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3262 #define SH_B3(eax) (eax == 0xf51)
1582 eb879d43ab47 6323525 Mutual exclusion primitives don't work as expected on Opteron systems kchow parents: 1414 diff changeset	3263 #define B(eax) (SH_B0(eax) \|\| SH_B3(eax))
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3264
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3265 #define SH_C0(eax) (eax == 0xf48 \|\| eax == 0xf58)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3266
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3267 #define SH_CG(eax) (eax == 0xf4a \|\| eax == 0xf5a \|\| eax == 0xf7a)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3268 #define DH_CG(eax) (eax == 0xfc0 \|\| eax == 0xfe0 \|\| eax == 0xff0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3269 #define CH_CG(eax) (eax == 0xf82 \|\| eax == 0xfb2)
1582 eb879d43ab47 6323525 Mutual exclusion primitives don't work as expected on Opteron systems kchow parents: 1414 diff changeset	3270 #define CG(eax) (SH_CG(eax) \|\| DH_CG(eax) \|\| CH_CG(eax))
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3271
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3272 #define SH_D0(eax) (eax == 0x10f40 \|\| eax == 0x10f50 \|\| eax == 0x10f70)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3273 #define DH_D0(eax) (eax == 0x10fc0 \|\| eax == 0x10ff0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3274 #define CH_D0(eax) (eax == 0x10f80 \|\| eax == 0x10fb0)
1582 eb879d43ab47 6323525 Mutual exclusion primitives don't work as expected on Opteron systems kchow parents: 1414 diff changeset	3275 #define D0(eax) (SH_D0(eax) \|\| DH_D0(eax) \|\| CH_D0(eax))
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3276
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3277 #define SH_E0(eax) (eax == 0x20f50 \|\| eax == 0x20f40 \|\| eax == 0x20f70)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3278 #define JH_E1(eax) (eax == 0x20f10) /* JH8_E0 had 0x20f30 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3279 #define DH_E3(eax) (eax == 0x20fc0 \|\| eax == 0x20ff0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3280 #define SH_E4(eax) (eax == 0x20f51 \|\| eax == 0x20f71)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3281 #define BH_E4(eax) (eax == 0x20fb1)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3282 #define SH_E5(eax) (eax == 0x20f42)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3283 #define DH_E6(eax) (eax == 0x20ff2 \|\| eax == 0x20fc2)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3284 #define JH_E6(eax) (eax == 0x20f12 \|\| eax == 0x20f32)
1582 eb879d43ab47 6323525 Mutual exclusion primitives don't work as expected on Opteron systems kchow parents: 1414 diff changeset	3285 #define EX(eax) (SH_E0(eax) \|\| JH_E1(eax) \|\| DH_E3(eax) \|\| \
eb879d43ab47 6323525 Mutual exclusion primitives don't work as expected on Opteron systems kchow parents: 1414 diff changeset	3286 SH_E4(eax) \|\| BH_E4(eax) \|\| SH_E5(eax) \|\| \
eb879d43ab47 6323525 Mutual exclusion primitives don't work as expected on Opteron systems kchow parents: 1414 diff changeset	3287 DH_E6(eax) \|\| JH_E6(eax))
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3288
6691 f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3289 #define DR_AX(eax) (eax == 0x100f00 \|\| eax == 0x100f01 \|\| eax == 0x100f02)
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3290 #define DR_B0(eax) (eax == 0x100f20)
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3291 #define DR_B1(eax) (eax == 0x100f21)
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3292 #define DR_BA(eax) (eax == 0x100f2a)
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3293 #define DR_B2(eax) (eax == 0x100f22)
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3294 #define DR_B3(eax) (eax == 0x100f23)
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3295 #define RB_C0(eax) (eax == 0x100f40)
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3296
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3297 switch (erratum) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3298 case 1:
4265 6be078c4d3b4 6555108 workarounds being applied for errata not present in greyhound processors kchow parents: 3779 diff changeset	3299 return (cpi->cpi_family < 0x10);
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3300 case 51: /* what does the asterisk mean? */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3301 return (B(eax) \|\| SH_C0(eax) \|\| CG(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3302 case 52:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3303 return (B(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3304 case 57:
6691 f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3305 return (cpi->cpi_family <= 0x11);
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3306 case 58:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3307 return (B(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3308 case 60:
6691 f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3309 return (cpi->cpi_family <= 0x11);
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3310 case 61:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3311 case 62:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3312 case 63:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3313 case 64:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3314 case 65:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3315 case 66:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3316 case 68:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3317 case 69:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3318 case 70:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3319 case 71:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3320 return (B(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3321 case 72:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3322 return (SH_B0(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3323 case 74:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3324 return (B(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3325 case 75:
4265 6be078c4d3b4 6555108 workarounds being applied for errata not present in greyhound processors kchow parents: 3779 diff changeset	3326 return (cpi->cpi_family < 0x10);
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3327 case 76:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3328 return (B(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3329 case 77:
6691 f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3330 return (cpi->cpi_family <= 0x11);
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3331 case 78:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3332 return (B(eax) \|\| SH_C0(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3333 case 79:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3334 return (B(eax) \|\| SH_C0(eax) \|\| CG(eax) \|\| D0(eax) \|\| EX(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3335 case 80:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3336 case 81:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3337 case 82:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3338 return (B(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3339 case 83:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3340 return (B(eax) \|\| SH_C0(eax) \|\| CG(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3341 case 85:
4265 6be078c4d3b4 6555108 workarounds being applied for errata not present in greyhound processors kchow parents: 3779 diff changeset	3342 return (cpi->cpi_family < 0x10);
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3343 case 86:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3344 return (SH_C0(eax) \|\| CG(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3345 case 88:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3346 #if !defined(__amd64)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3347 return (0);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3348 #else
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3349 return (B(eax) \|\| SH_C0(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3350 #endif
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3351 case 89:
4265 6be078c4d3b4 6555108 workarounds being applied for errata not present in greyhound processors kchow parents: 3779 diff changeset	3352 return (cpi->cpi_family < 0x10);
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3353 case 90:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3354 return (B(eax) \|\| SH_C0(eax) \|\| CG(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3355 case 91:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3356 case 92:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3357 return (B(eax) \|\| SH_C0(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3358 case 93:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3359 return (SH_C0(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3360 case 94:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3361 return (B(eax) \|\| SH_C0(eax) \|\| CG(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3362 case 95:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3363 #if !defined(__amd64)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3364 return (0);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3365 #else
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3366 return (B(eax) \|\| SH_C0(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3367 #endif
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3368 case 96:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3369 return (B(eax) \|\| SH_C0(eax) \|\| CG(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3370 case 97:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3371 case 98:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3372 return (SH_C0(eax) \|\| CG(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3373 case 99:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3374 return (B(eax) \|\| SH_C0(eax) \|\| CG(eax) \|\| D0(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3375 case 100:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3376 return (B(eax) \|\| SH_C0(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3377 case 101:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3378 case 103:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3379 return (B(eax) \|\| SH_C0(eax) \|\| CG(eax) \|\| D0(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3380 case 104:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3381 return (SH_C0(eax) \|\| CG(eax) \|\| D0(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3382 case 105:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3383 case 106:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3384 case 107:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3385 return (B(eax) \|\| SH_C0(eax) \|\| CG(eax) \|\| D0(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3386 case 108:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3387 return (DH_CG(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3388 case 109:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3389 return (SH_C0(eax) \|\| CG(eax) \|\| D0(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3390 case 110:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3391 return (D0(eax) \|\| EX(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3392 case 111:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3393 return (CG(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3394 case 112:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3395 return (B(eax) \|\| SH_C0(eax) \|\| CG(eax) \|\| D0(eax) \|\| EX(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3396 case 113:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3397 return (eax == 0x20fc0);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3398 case 114:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3399 return (SH_E0(eax) \|\| JH_E1(eax) \|\| DH_E3(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3400 case 115:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3401 return (SH_E0(eax) \|\| JH_E1(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3402 case 116:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3403 return (SH_E0(eax) \|\| JH_E1(eax) \|\| DH_E3(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3404 case 117:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3405 return (B(eax) \|\| SH_C0(eax) \|\| CG(eax) \|\| D0(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3406 case 118:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3407 return (SH_E0(eax) \|\| JH_E1(eax) \|\| SH_E4(eax) \|\| BH_E4(eax) \|\|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3408 JH_E6(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3409 case 121:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3410 return (B(eax) \|\| SH_C0(eax) \|\| CG(eax) \|\| D0(eax) \|\| EX(eax));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3411 case 122:
6691 f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3412 return (cpi->cpi_family < 0x10 \|\| cpi->cpi_family == 0x11);
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3413 case 123:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3414 return (JH_E1(eax) \|\| BH_E4(eax) \|\| JH_E6(eax));
359 a88cb999e7ec 6288246 amd64 kernel needs to detect AMD Opteron erratum 131 kucharsk parents: 0 diff changeset	3415 case 131:
4265 6be078c4d3b4 6555108 workarounds being applied for errata not present in greyhound processors kchow parents: 3779 diff changeset	3416 return (cpi->cpi_family < 0x10);
938 2d438f28c673 6336786 time doesn't fly when CPUs are not having fun esaxe parents: 789 diff changeset	3417 case 6336786:
2d438f28c673 6336786 time doesn't fly when CPUs are not having fun esaxe parents: 789 diff changeset	3418 /*
2d438f28c673 6336786 time doesn't fly when CPUs are not having fun esaxe parents: 789 diff changeset	3419 * Test for AdvPowerMgmtInfo.TscPStateInvariant
4265 6be078c4d3b4 6555108 workarounds being applied for errata not present in greyhound processors kchow parents: 3779 diff changeset	3420 * if this is a K8 family or newer processor
938 2d438f28c673 6336786 time doesn't fly when CPUs are not having fun esaxe parents: 789 diff changeset	3421 */
2d438f28c673 6336786 time doesn't fly when CPUs are not having fun esaxe parents: 789 diff changeset	3422 if (CPI_FAMILY(cpi) == 0xf) {
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	3423 struct cpuid_regs regs;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	3424 regs.cp_eax = 0x80000007;
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	3425 (void) __cpuid_insn(&regs);
9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	3426 return (!(regs.cp_edx & 0x100));
938 2d438f28c673 6336786 time doesn't fly when CPUs are not having fun esaxe parents: 789 diff changeset	3427 }
2d438f28c673 6336786 time doesn't fly when CPUs are not having fun esaxe parents: 789 diff changeset	3428 return (0);
1582 eb879d43ab47 6323525 Mutual exclusion primitives don't work as expected on Opteron systems kchow parents: 1414 diff changeset	3429 case 6323525:
eb879d43ab47 6323525 Mutual exclusion primitives don't work as expected on Opteron systems kchow parents: 1414 diff changeset	3430 return (((((eax >> 12) & 0xff00) + (eax & 0xf00)) \|
eb879d43ab47 6323525 Mutual exclusion primitives don't work as expected on Opteron systems kchow parents: 1414 diff changeset	3431 (((eax >> 4) & 0xf) \| ((eax >> 12) & 0xf0))) < 0xf40);
eb879d43ab47 6323525 Mutual exclusion primitives don't work as expected on Opteron systems kchow parents: 1414 diff changeset	3432
6691 f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3433 case 6671130:
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3434 /*
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3435 * check for processors (pre-Shanghai) that do not provide
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3436 * optimal management of 1gb ptes in its tlb.
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3437 */
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3438 return (cpi->cpi_family == 0x10 && cpi->cpi_model < 4);
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3439
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3440 case 298:
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3441 return (DR_AX(eax) \|\| DR_B0(eax) \|\| DR_B1(eax) \|\| DR_BA(eax) \|\|
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3442 DR_B2(eax) \|\| RB_C0(eax));
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3443
13651 af464d8d3a31 2449 Add workaround for AMD K10 CPU erratum 721 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13498 diff changeset	3444 case 721:
af464d8d3a31 2449 Add workaround for AMD K10 CPU erratum 721 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13498 diff changeset	3445 #if defined(__amd64)
af464d8d3a31 2449 Add workaround for AMD K10 CPU erratum 721 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13498 diff changeset	3446 return (cpi->cpi_family == 0x10 \|\| cpi->cpi_family == 0x12);
af464d8d3a31 2449 Add workaround for AMD K10 CPU erratum 721 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13498 diff changeset	3447 #else
af464d8d3a31 2449 Add workaround for AMD K10 CPU erratum 721 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13498 diff changeset	3448 return (0);
af464d8d3a31 2449 Add workaround for AMD K10 CPU erratum 721 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13498 diff changeset	3449 #endif
af464d8d3a31 2449 Add workaround for AMD K10 CPU erratum 721 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13498 diff changeset	3450
6691 f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3451 default:
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3452 return (-1);
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3453
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3454 }
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3455 }
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3456
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3457 /*
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3458 * Determine if specified erratum is present via OSVW (OS Visible Workaround).
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3459 * Return 1 if erratum is present, 0 if not present and -1 if indeterminate.
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3460 */
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3461 int
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3462 osvw_opteron_erratum(cpu_t *cpu, uint_t erratum)
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3463 {
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3464 struct cpuid_info *cpi;
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3465 uint_t osvwid;
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3466 static int osvwfeature = -1;
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3467 uint64_t osvwlength;
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3468
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3469
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3470 cpi = cpu->cpu_m.mcpu_cpi;
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3471
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3472 /* confirm OSVW supported */
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3473 if (osvwfeature == -1) {
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3474 osvwfeature = cpi->cpi_extd[1].cp_ecx & CPUID_AMD_ECX_OSVW;
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3475 } else {
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3476 /* assert that osvw feature setting is consistent on all cpus */
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3477 ASSERT(osvwfeature ==
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3478 (cpi->cpi_extd[1].cp_ecx & CPUID_AMD_ECX_OSVW));
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3479 }
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3480 if (!osvwfeature)
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3481 return (-1);
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3482
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3483 osvwlength = rdmsr(MSR_AMD_OSVW_ID_LEN) & OSVW_ID_LEN_MASK;
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3484
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3485 switch (erratum) {
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3486 case 298: /* osvwid is 0 */
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3487 osvwid = 0;
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3488 if (osvwlength <= (uint64_t)osvwid) {
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3489 /* osvwid 0 is unknown */
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3490 return (-1);
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3491 }
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3492
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3493 /*
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3494 * Check the OSVW STATUS MSR to determine the state
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3495 * of the erratum where:
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3496 * 0 - fixed by HW
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3497 * 1 - BIOS has applied the workaround when BIOS
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3498 * workaround is available. (Or for other errata,
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3499 * OS workaround is required.)
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3500 * For a value of 1, caller will confirm that the
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3501 * erratum 298 workaround has indeed been applied by BIOS.
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3502 *
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3503 * A 1 may be set in cpus that have a HW fix
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3504 * in a mixed cpu system. Regarding erratum 298:
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3505 * In a multiprocessor platform, the workaround above
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3506 * should be applied to all processors regardless of
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3507 * silicon revision when an affected processor is
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3508 * present.
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3509 */
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3510
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3511 return (rdmsr(MSR_AMD_OSVW_STATUS +
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3512 (osvwid / OSVW_ID_CNT_PER_MSR)) &
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3513 (1ULL << (osvwid % OSVW_ID_CNT_PER_MSR)));
f8848c7acc9e 6671130 Shanghai provides better TLB management for 1GB pages kchow parents: 6671 diff changeset	3514
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3515 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3516 return (-1);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3517 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3518 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3519
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3520 static const char assoc_str[] = "associativity";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3521 static const char line_str[] = "line-size";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3522 static const char size_str[] = "size";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3523
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3524 static void
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3525 add_cache_prop(dev_info_t devi, const char label, const char *type,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3526 uint32_t val)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3527 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3528 char buf[128];
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3529
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3530 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3531 * ndi_prop_update_int() is used because it is desirable for
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3532 * DDI_PROP_HW_DEF and DDI_PROP_DONTSLEEP to be set.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3533 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3534 if (snprintf(buf, sizeof (buf), "%s-%s", label, type) < sizeof (buf))
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3535 (void) ndi_prop_update_int(DDI_DEV_T_NONE, devi, buf, val);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3536 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3537
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3538 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3539 * Intel-style cache/tlb description
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3540 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3541 * Standard cpuid level 2 gives a randomly ordered
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3542 * selection of tags that index into a table that describes
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3543 * cache and tlb properties.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3544 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3545
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3546 static const char l1_icache_str[] = "l1-icache";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3547 static const char l1_dcache_str[] = "l1-dcache";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3548 static const char l2_cache_str[] = "l2-cache";
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	3549 static const char l3_cache_str[] = "l3-cache";
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3550 static const char itlb4k_str[] = "itlb-4K";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3551 static const char dtlb4k_str[] = "dtlb-4K";
6964 3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3552 static const char itlb2M_str[] = "itlb-2M";
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3553 static const char itlb4M_str[] = "itlb-4M";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3554 static const char dtlb4M_str[] = "dtlb-4M";
6334 950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3555 static const char dtlb24_str[] = "dtlb0-2M-4M";
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3556 static const char itlb424_str[] = "itlb-4K-2M-4M";
6334 950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3557 static const char itlb24_str[] = "itlb-2M-4M";
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3558 static const char dtlb44_str[] = "dtlb-4K-4M";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3559 static const char sl1_dcache_str[] = "sectored-l1-dcache";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3560 static const char sl2_cache_str[] = "sectored-l2-cache";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3561 static const char itrace_str[] = "itrace-cache";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3562 static const char sl3_cache_str[] = "sectored-l3-cache";
6334 950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3563 static const char sh_l2_tlb4k_str[] = "shared-l2-tlb-4k";
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3564
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3565 static const struct cachetab {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3566 uint8_t ct_code;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3567 uint8_t ct_assoc;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3568 uint16_t ct_line_size;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3569 size_t ct_size;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3570 const char *ct_label;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3571 } intel_ctab[] = {
6964 3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3572 /*
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3573 * maintain descending order!
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3574 *
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3575 * Codes ignored - Reason
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3576 * ----------------------
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3577 * 40H - intel_cpuid_4_cache_info() disambiguates l2/l3 cache
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3578 * f0H/f1H - Currently we do not interpret prefetch size by design
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3579 */
6334 950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3580 { 0xe4, 16, 64, 810241024, l3_cache_str},
950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3581 { 0xe3, 16, 64, 410241024, l3_cache_str},
950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3582 { 0xe2, 16, 64, 210241024, l3_cache_str},
950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3583 { 0xde, 12, 64, 610241024, l3_cache_str},
950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3584 { 0xdd, 12, 64, 310241024, l3_cache_str},
950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3585 { 0xdc, 12, 64, ((110241024)+(512*1024)), l3_cache_str},
950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3586 { 0xd8, 8, 64, 410241024, l3_cache_str},
950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3587 { 0xd7, 8, 64, 210241024, l3_cache_str},
950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3588 { 0xd6, 8, 64, 110241024, l3_cache_str},
950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3589 { 0xd2, 4, 64, 210241024, l3_cache_str},
950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3590 { 0xd1, 4, 64, 110241024, l3_cache_str},
950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3591 { 0xd0, 4, 64, 512*1024, l3_cache_str},
950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3592 { 0xca, 4, 0, 512, sh_l2_tlb4k_str},
6964 3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3593 { 0xc0, 4, 0, 8, dtlb44_str },
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3594 { 0xba, 4, 0, 64, dtlb4k_str },
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	3595 { 0xb4, 4, 0, 256, dtlb4k_str },
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3596 { 0xb3, 4, 0, 128, dtlb4k_str },
6334 950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3597 { 0xb2, 4, 0, 64, itlb4k_str },
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3598 { 0xb0, 4, 0, 128, itlb4k_str },
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3599 { 0x87, 8, 64, 1024*1024, l2_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3600 { 0x86, 4, 64, 512*1024, l2_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3601 { 0x85, 8, 32, 210241024, l2_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3602 { 0x84, 8, 32, 1024*1024, l2_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3603 { 0x83, 8, 32, 512*1024, l2_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3604 { 0x82, 8, 32, 256*1024, l2_cache_str},
6964 3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3605 { 0x80, 8, 64, 512*1024, l2_cache_str},
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3606 { 0x7f, 2, 64, 512*1024, l2_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3607 { 0x7d, 8, 64, 210241024, sl2_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3608 { 0x7c, 8, 64, 1024*1024, sl2_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3609 { 0x7b, 8, 64, 512*1024, sl2_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3610 { 0x7a, 8, 64, 256*1024, sl2_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3611 { 0x79, 8, 64, 128*1024, sl2_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3612 { 0x78, 8, 64, 1024*1024, l2_cache_str},
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	3613 { 0x73, 8, 0, 64*1024, itrace_str},
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3614 { 0x72, 8, 0, 32*1024, itrace_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3615 { 0x71, 8, 0, 16*1024, itrace_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3616 { 0x70, 8, 0, 12*1024, itrace_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3617 { 0x68, 4, 64, 32*1024, sl1_dcache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3618 { 0x67, 4, 64, 16*1024, sl1_dcache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3619 { 0x66, 4, 64, 8*1024, sl1_dcache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3620 { 0x60, 8, 64, 16*1024, sl1_dcache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3621 { 0x5d, 0, 0, 256, dtlb44_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3622 { 0x5c, 0, 0, 128, dtlb44_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3623 { 0x5b, 0, 0, 64, dtlb44_str},
6334 950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3624 { 0x5a, 4, 0, 32, dtlb24_str},
6964 3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3625 { 0x59, 0, 0, 16, dtlb4k_str},
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3626 { 0x57, 4, 0, 16, dtlb4k_str},
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3627 { 0x56, 4, 0, 16, dtlb4M_str},
6334 950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3628 { 0x55, 0, 0, 7, itlb24_str},
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3629 { 0x52, 0, 0, 256, itlb424_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3630 { 0x51, 0, 0, 128, itlb424_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3631 { 0x50, 0, 0, 64, itlb424_str},
6964 3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3632 { 0x4f, 0, 0, 32, itlb4k_str},
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3633 { 0x4e, 24, 64, 610241024, l2_cache_str},
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	3634 { 0x4d, 16, 64, 1610241024, l3_cache_str},
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	3635 { 0x4c, 12, 64, 1210241024, l3_cache_str},
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	3636 { 0x4b, 16, 64, 810241024, l3_cache_str},
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	3637 { 0x4a, 12, 64, 610241024, l3_cache_str},
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	3638 { 0x49, 16, 64, 410241024, l3_cache_str},
6964 3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3639 { 0x48, 12, 64, 310241024, l2_cache_str},
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	3640 { 0x47, 8, 64, 810241024, l3_cache_str},
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	3641 { 0x46, 4, 64, 410241024, l3_cache_str},
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3642 { 0x45, 4, 32, 210241024, l2_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3643 { 0x44, 4, 32, 1024*1024, l2_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3644 { 0x43, 4, 32, 512*1024, l2_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3645 { 0x42, 4, 32, 256*1024, l2_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3646 { 0x41, 4, 32, 128*1024, l2_cache_str},
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	3647 { 0x3e, 4, 64, 512*1024, sl2_cache_str},
5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	3648 { 0x3d, 6, 64, 384*1024, sl2_cache_str},
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3649 { 0x3c, 4, 64, 256*1024, sl2_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3650 { 0x3b, 2, 64, 128*1024, sl2_cache_str},
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	3651 { 0x3a, 6, 64, 192*1024, sl2_cache_str},
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3652 { 0x39, 4, 64, 128*1024, sl2_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3653 { 0x30, 8, 64, 32*1024, l1_icache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3654 { 0x2c, 8, 64, 32*1024, l1_dcache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3655 { 0x29, 8, 64, 4096*1024, sl3_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3656 { 0x25, 8, 64, 2048*1024, sl3_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3657 { 0x23, 8, 64, 1024*1024, sl3_cache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3658 { 0x22, 4, 64, 512*1024, sl3_cache_str},
6964 3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3659 { 0x0e, 6, 64, 24*1024, l1_dcache_str},
6334 950d3f34a725 6662206 Add new CPUID.2 descriptors for upcoming Intel processor ksadhukh parents: 6317 diff changeset	3660 { 0x0d, 4, 32, 16*1024, l1_dcache_str},
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3661 { 0x0c, 4, 32, 16*1024, l1_dcache_str},
3446 5903aece022d PSARC 2006/469 EOF and removal of eeprom -I mrj parents: 3434 diff changeset	3662 { 0x0b, 4, 0, 4, itlb4M_str},
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3663 { 0x0a, 2, 32, 8*1024, l1_dcache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3664 { 0x08, 4, 32, 16*1024, l1_icache_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3665 { 0x06, 4, 32, 8*1024, l1_icache_str},
6964 3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3666 { 0x05, 4, 0, 32, dtlb4M_str},
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3667 { 0x04, 4, 0, 8, dtlb4M_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3668 { 0x03, 4, 0, 64, dtlb4k_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3669 { 0x02, 4, 0, 2, itlb4M_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3670 { 0x01, 4, 0, 32, itlb4k_str},
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3671 { 0 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3672 };
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3673
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3674 static const struct cachetab cyrix_ctab[] = {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3675 { 0x70, 4, 0, 32, "tlb-4K" },
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3676 { 0x80, 4, 16, 16*1024, "l1-cache" },
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3677 { 0 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3678 };
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3679
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3680 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3681 * Search a cache table for a matching entry
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3682 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3683 static const struct cachetab *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3684 find_cacheent(const struct cachetab *ct, uint_t code)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3685 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3686 if (code != 0) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3687 for (; ct->ct_code != 0; ct++)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3688 if (ct->ct_code <= code)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3689 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3690 if (ct->ct_code == code)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3691 return (ct);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3692 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3693 return (NULL);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3694 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3695
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3696 /*
5438 41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3697 * Populate cachetab entry with L2 or L3 cache-information using
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3698 * cpuid function 4. This function is called from intel_walk_cacheinfo()
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3699 * when descriptor 0x49 is encountered. It returns 0 if no such cache
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3700 * information is found.
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3701 */
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3702 static int
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3703 intel_cpuid_4_cache_info(struct cachetab ct, struct cpuid_info cpi)
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3704 {
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3705 uint32_t level, i;
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3706 int ret = 0;
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3707
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3708 for (i = 0; i < cpi->cpi_std_4_size; i++) {
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3709 level = CPI_CACHE_LVL(cpi->cpi_std_4[i]);
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3710
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3711 if (level == 2 \|\| level == 3) {
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3712 ct->ct_assoc = CPI_CACHE_WAYS(cpi->cpi_std_4[i]) + 1;
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3713 ct->ct_line_size =
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3714 CPI_CACHE_COH_LN_SZ(cpi->cpi_std_4[i]) + 1;
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3715 ct->ct_size = ct->ct_assoc *
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3716 (CPI_CACHE_PARTS(cpi->cpi_std_4[i]) + 1) *
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3717 ct->ct_line_size *
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3718 (cpi->cpi_std_4[i]->cp_ecx + 1);
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3719
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3720 if (level == 2) {
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3721 ct->ct_label = l2_cache_str;
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3722 } else if (level == 3) {
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3723 ct->ct_label = l3_cache_str;
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3724 }
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3725 ret = 1;
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3726 }
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3727 }
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3728
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3729 return (ret);
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3730 }
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3731
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3732 /*
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3733 * Walk the cacheinfo descriptor, applying 'func' to every valid element
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3734 * The walk is terminated if the walker returns non-zero.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3735 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3736 static void
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3737 intel_walk_cacheinfo(struct cpuid_info *cpi,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3738 void arg, int (func)(void , const struct cachetab ))
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3739 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3740 const struct cachetab *ct;
6964 3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3741 struct cachetab des_49_ct, des_b1_ct;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3742 uint8_t *dp;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3743 int i;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3744
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3745 if ((dp = cpi->cpi_cacheinfo) == NULL)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3746 return;
4797 2ebe22df4dfc 6563585 prtconf reports wrong cache-level on x86 systems having 4MB (associative=16, line-size=64) L2 cache ksadhukh parents: 4636 diff changeset	3747 for (i = 0; i < cpi->cpi_ncache; i++, dp++) {
2ebe22df4dfc 6563585 prtconf reports wrong cache-level on x86 systems having 4MB (associative=16, line-size=64) L2 cache ksadhukh parents: 4636 diff changeset	3748 /*
2ebe22df4dfc 6563585 prtconf reports wrong cache-level on x86 systems having 4MB (associative=16, line-size=64) L2 cache ksadhukh parents: 4636 diff changeset	3749 * For overloaded descriptor 0x49 we use cpuid function 4
5438 41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3750 * if supported by the current processor, to create
4797 2ebe22df4dfc 6563585 prtconf reports wrong cache-level on x86 systems having 4MB (associative=16, line-size=64) L2 cache ksadhukh parents: 4636 diff changeset	3751 * cache information.
6964 3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3752 * For overloaded descriptor 0xb1 we use X86_PAE flag
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3753 * to disambiguate the cache information.
4797 2ebe22df4dfc 6563585 prtconf reports wrong cache-level on x86 systems having 4MB (associative=16, line-size=64) L2 cache ksadhukh parents: 4636 diff changeset	3754 */
5438 41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3755 if (*dp == 0x49 && cpi->cpi_maxeax >= 0x4 &&
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3756 intel_cpuid_4_cache_info(&des_49_ct, cpi) == 1) {
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3757 ct = &des_49_ct;
6964 3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3758 } else if (*dp == 0xb1) {
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3759 des_b1_ct.ct_code = 0xb1;
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3760 des_b1_ct.ct_assoc = 4;
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3761 des_b1_ct.ct_line_size = 0;
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	3762 if (is_x86_feature(x86_featureset, X86FSET_PAE)) {
6964 3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3763 des_b1_ct.ct_size = 8;
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3764 des_b1_ct.ct_label = itlb2M_str;
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3765 } else {
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3766 des_b1_ct.ct_size = 4;
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3767 des_b1_ct.ct_label = itlb4M_str;
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3768 }
3eb8a0c8b90a 6667592 Mismatch between intel_ctab array and processor specification for the cache descriptors vd224797 parents: 6691 diff changeset	3769 ct = &des_b1_ct;
5438 41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3770 } else {
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3771 if ((ct = find_cacheent(intel_ctab, *dp)) == NULL) {
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3772 continue;
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3773 }
4797 2ebe22df4dfc 6563585 prtconf reports wrong cache-level on x86 systems having 4MB (associative=16, line-size=64) L2 cache ksadhukh parents: 4636 diff changeset	3774 }
2ebe22df4dfc 6563585 prtconf reports wrong cache-level on x86 systems having 4MB (associative=16, line-size=64) L2 cache ksadhukh parents: 4636 diff changeset	3775
5438 41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3776 if (func(arg, ct) != 0) {
41d8edfa90d7 6603986 Installing a Linux zone on an Intel blade causes a panic ksadhukh parents: 5349 diff changeset	3777 break;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3778 }
4797 2ebe22df4dfc 6563585 prtconf reports wrong cache-level on x86 systems having 4MB (associative=16, line-size=64) L2 cache ksadhukh parents: 4636 diff changeset	3779 }
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3780 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3781
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3782 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3783 * (Like the Intel one, except for Cyrix CPUs)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3784 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3785 static void
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3786 cyrix_walk_cacheinfo(struct cpuid_info *cpi,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3787 void arg, int (func)(void , const struct cachetab ))
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3788 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3789 const struct cachetab *ct;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3790 uint8_t *dp;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3791 int i;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3792
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3793 if ((dp = cpi->cpi_cacheinfo) == NULL)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3794 return;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3795 for (i = 0; i < cpi->cpi_ncache; i++, dp++) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3796 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3797 * Search Cyrix-specific descriptor table first ..
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3798 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3799 if ((ct = find_cacheent(cyrix_ctab, *dp)) != NULL) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3800 if (func(arg, ct) != 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3801 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3802 continue;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3803 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3804 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3805 * .. else fall back to the Intel one
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3806 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3807 if ((ct = find_cacheent(intel_ctab, *dp)) != NULL) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3808 if (func(arg, ct) != 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3809 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3810 continue;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3811 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3812 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3813 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3814
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3815 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3816 * A cacheinfo walker that adds associativity, line-size, and size properties
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3817 * to the devinfo node it is passed as an argument.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3818 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3819 static int
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3820 add_cacheent_props(void arg, const struct cachetab ct)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3821 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3822 dev_info_t *devi = arg;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3823
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3824 add_cache_prop(devi, ct->ct_label, assoc_str, ct->ct_assoc);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3825 if (ct->ct_line_size != 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3826 add_cache_prop(devi, ct->ct_label, line_str,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3827 ct->ct_line_size);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3828 add_cache_prop(devi, ct->ct_label, size_str, ct->ct_size);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3829 return (0);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3830 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3831
4797 2ebe22df4dfc 6563585 prtconf reports wrong cache-level on x86 systems having 4MB (associative=16, line-size=64) L2 cache ksadhukh parents: 4636 diff changeset	3832
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3833 static const char fully_assoc[] = "fully-associative?";
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3834
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3835 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3836 * AMD style cache/tlb description
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3837 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3838 * Extended functions 5 and 6 directly describe properties of
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3839 * tlbs and various cache levels.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3840 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3841 static void
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3842 add_amd_assoc(dev_info_t devi, const char label, uint_t assoc)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3843 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3844 switch (assoc) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3845 case 0: /* reserved; ignore */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3846 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3847 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3848 add_cache_prop(devi, label, assoc_str, assoc);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3849 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3850 case 0xff:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3851 add_cache_prop(devi, label, fully_assoc, 1);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3852 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3853 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3854 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3855
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3856 static void
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3857 add_amd_tlb(dev_info_t devi, const char label, uint_t assoc, uint_t size)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3858 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3859 if (size == 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3860 return;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3861 add_cache_prop(devi, label, size_str, size);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3862 add_amd_assoc(devi, label, assoc);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3863 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3864
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3865 static void
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3866 add_amd_cache(dev_info_t devi, const char label,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3867 uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3868 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3869 if (size == 0 \|\| line_size == 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3870 return;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3871 add_amd_assoc(devi, label, assoc);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3872 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3873 * Most AMD parts have a sectored cache. Multiple cache lines are
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3874 * associated with each tag. A sector consists of all cache lines
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3875 * associated with a tag. For example, the AMD K6-III has a sector
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3876 * size of 2 cache lines per tag.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3877 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3878 if (lines_per_tag != 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3879 add_cache_prop(devi, label, "lines-per-tag", lines_per_tag);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3880 add_cache_prop(devi, label, line_str, line_size);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3881 add_cache_prop(devi, label, size_str, size * 1024);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3882 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3883
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3884 static void
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3885 add_amd_l2_assoc(dev_info_t devi, const char label, uint_t assoc)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3886 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3887 switch (assoc) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3888 case 0: /* off */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3889 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3890 case 1:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3891 case 2:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3892 case 4:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3893 add_cache_prop(devi, label, assoc_str, assoc);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3894 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3895 case 6:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3896 add_cache_prop(devi, label, assoc_str, 8);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3897 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3898 case 8:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3899 add_cache_prop(devi, label, assoc_str, 16);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3900 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3901 case 0xf:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3902 add_cache_prop(devi, label, fully_assoc, 1);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3903 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3904 default: /* reserved; ignore */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3905 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3906 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3907 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3908
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3909 static void
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3910 add_amd_l2_tlb(dev_info_t devi, const char label, uint_t assoc, uint_t size)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3911 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3912 if (size == 0 \|\| assoc == 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3913 return;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3914 add_amd_l2_assoc(devi, label, assoc);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3915 add_cache_prop(devi, label, size_str, size);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3916 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3917
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3918 static void
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3919 add_amd_l2_cache(dev_info_t devi, const char label,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3920 uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3921 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3922 if (size == 0 \|\| assoc == 0 \|\| line_size == 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3923 return;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3924 add_amd_l2_assoc(devi, label, assoc);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3925 if (lines_per_tag != 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3926 add_cache_prop(devi, label, "lines-per-tag", lines_per_tag);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3927 add_cache_prop(devi, label, line_str, line_size);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3928 add_cache_prop(devi, label, size_str, size * 1024);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3929 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3930
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3931 static void
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3932 amd_cache_info(struct cpuid_info cpi, dev_info_t devi)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3933 {
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	3934 struct cpuid_regs *cp;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3935
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3936 if (cpi->cpi_xmaxeax < 0x80000005)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3937 return;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3938 cp = &cpi->cpi_extd[5];
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3939
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3940 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3941 * 4M/2M L1 TLB configuration
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3942 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3943 * We report the size for 2M pages because AMD uses two
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3944 * TLB entries for one 4M page.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3945 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3946 add_amd_tlb(devi, "dtlb-2M",
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3947 BITX(cp->cp_eax, 31, 24), BITX(cp->cp_eax, 23, 16));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3948 add_amd_tlb(devi, "itlb-2M",
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3949 BITX(cp->cp_eax, 15, 8), BITX(cp->cp_eax, 7, 0));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3950
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3951 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3952 * 4K L1 TLB configuration
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3953 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3954
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3955 switch (cpi->cpi_vendor) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3956 uint_t nentries;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3957 case X86_VENDOR_TM:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3958 if (cpi->cpi_family >= 5) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3959 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3960 * Crusoe processors have 256 TLB entries, but
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3961 * cpuid data format constrains them to only
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3962 * reporting 255 of them.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3963 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3964 if ((nentries = BITX(cp->cp_ebx, 23, 16)) == 255)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3965 nentries = 256;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3966 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3967 * Crusoe processors also have a unified TLB
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3968 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3969 add_amd_tlb(devi, "tlb-4K", BITX(cp->cp_ebx, 31, 24),
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3970 nentries);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3971 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3972 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3973 /FALLTHROUGH/
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3974 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3975 add_amd_tlb(devi, itlb4k_str,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3976 BITX(cp->cp_ebx, 31, 24), BITX(cp->cp_ebx, 23, 16));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3977 add_amd_tlb(devi, dtlb4k_str,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3978 BITX(cp->cp_ebx, 15, 8), BITX(cp->cp_ebx, 7, 0));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3979 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3980 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3981
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3982 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3983 * data L1 cache configuration
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3984 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3985
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3986 add_amd_cache(devi, l1_dcache_str,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3987 BITX(cp->cp_ecx, 31, 24), BITX(cp->cp_ecx, 23, 16),
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3988 BITX(cp->cp_ecx, 15, 8), BITX(cp->cp_ecx, 7, 0));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3989
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3990 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3991 * code L1 cache configuration
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3992 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3993
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3994 add_amd_cache(devi, l1_icache_str,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3995 BITX(cp->cp_edx, 31, 24), BITX(cp->cp_edx, 23, 16),
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3996 BITX(cp->cp_edx, 15, 8), BITX(cp->cp_edx, 7, 0));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3997
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3998 if (cpi->cpi_xmaxeax < 0x80000006)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	3999 return;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4000 cp = &cpi->cpi_extd[6];
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4001
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4002 /* Check for a unified L2 TLB for large pages */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4003
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4004 if (BITX(cp->cp_eax, 31, 16) == 0)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4005 add_amd_l2_tlb(devi, "l2-tlb-2M",
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4006 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4007 else {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4008 add_amd_l2_tlb(devi, "l2-dtlb-2M",
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4009 BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4010 add_amd_l2_tlb(devi, "l2-itlb-2M",
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4011 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4012 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4013
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4014 /* Check for a unified L2 TLB for 4K pages */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4015
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4016 if (BITX(cp->cp_ebx, 31, 16) == 0) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4017 add_amd_l2_tlb(devi, "l2-tlb-4K",
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4018 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4019 } else {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4020 add_amd_l2_tlb(devi, "l2-dtlb-4K",
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4021 BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4022 add_amd_l2_tlb(devi, "l2-itlb-4K",
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4023 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4024 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4025
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4026 add_amd_l2_cache(devi, l2_cache_str,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4027 BITX(cp->cp_ecx, 31, 16), BITX(cp->cp_ecx, 15, 12),
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4028 BITX(cp->cp_ecx, 11, 8), BITX(cp->cp_ecx, 7, 0));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4029 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4030
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4031 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4032 * There are two basic ways that the x86 world describes it cache
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4033 * and tlb architecture - Intel's way and AMD's way.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4034 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4035 * Return which flavor of cache architecture we should use
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4036 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4037 static int
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4038 x86_which_cacheinfo(struct cpuid_info *cpi)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4039 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4040 switch (cpi->cpi_vendor) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4041 case X86_VENDOR_Intel:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4042 if (cpi->cpi_maxeax >= 2)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4043 return (X86_VENDOR_Intel);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4044 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4045 case X86_VENDOR_AMD:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4046 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4047 * The K5 model 1 was the first part from AMD that reported
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4048 * cache sizes via extended cpuid functions.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4049 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4050 if (cpi->cpi_family > 5 \|\|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4051 (cpi->cpi_family == 5 && cpi->cpi_model >= 1))
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4052 return (X86_VENDOR_AMD);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4053 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4054 case X86_VENDOR_TM:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4055 if (cpi->cpi_family >= 5)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4056 return (X86_VENDOR_AMD);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4057 /FALLTHROUGH/
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4058 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4059 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4060 * If they have extended CPU data for 0x80000005
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4061 * then we assume they have AMD-format cache
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4062 * information.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4063 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4064 * If not, and the vendor happens to be Cyrix,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4065 * then try our-Cyrix specific handler.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4066 *
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4067 * If we're not Cyrix, then assume we're using Intel's
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4068 * table-driven format instead.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4069 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4070 if (cpi->cpi_xmaxeax >= 0x80000005)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4071 return (X86_VENDOR_AMD);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4072 else if (cpi->cpi_vendor == X86_VENDOR_Cyrix)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4073 return (X86_VENDOR_Cyrix);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4074 else if (cpi->cpi_maxeax >= 2)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4075 return (X86_VENDOR_Intel);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4076 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4077 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4078 return (-1);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4079 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4080
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4081 void
9652 6b40e106879c 6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot Michael Corcoran <Michael.Corcoran@Sun.COM> parents: 9482 diff changeset	4082 cpuid_set_cpu_properties(void *dip, processorid_t cpu_id,
6b40e106879c 6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot Michael Corcoran <Michael.Corcoran@Sun.COM> parents: 9482 diff changeset	4083 struct cpuid_info *cpi)
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4084 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4085 dev_info_t *cpu_devi;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4086 int create;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4087
9652 6b40e106879c 6815568 ACPICA enhancements for support of ACPI-based device enumeration earlier in boot Michael Corcoran <Michael.Corcoran@Sun.COM> parents: 9482 diff changeset	4088 cpu_devi = (dev_info_t *)dip;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4089
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4090 /* device_type */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4091 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4092 "device_type", "cpu");
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4093
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4094 /* reg */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4095 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4096 "reg", cpu_id);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4097
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4098 /* cpu-mhz, and clock-frequency */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4099 if (cpu_freq > 0) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4100 long long mul;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4101
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4102 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4103 "cpu-mhz", cpu_freq);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4104 if ((mul = cpu_freq * 1000000LL) <= INT_MAX)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4105 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4106 "clock-frequency", (int)mul);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4107 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4108
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	4109 if (!is_x86_feature(x86_featureset, X86FSET_CPUID)) {
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4110 return;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4111 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4112
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4113 /* vendor-id */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4114 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi,
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	4115 "vendor-id", cpi->cpi_vendorstr);
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4116
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4117 if (cpi->cpi_maxeax == 0) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4118 return;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4119 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4120
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4121 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4122 * family, model, and step
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4123 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4124 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	4125 "family", CPI_FAMILY(cpi));
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4126 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	4127 "cpu-model", CPI_MODEL(cpi));
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4128 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	4129 "stepping-id", CPI_STEP(cpi));
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4130
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4131 /* type */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4132 switch (cpi->cpi_vendor) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4133 case X86_VENDOR_Intel:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4134 create = 1;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4135 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4136 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4137 create = 0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4138 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4139 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4140 if (create)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4141 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	4142 "type", CPI_TYPE(cpi));
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4143
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4144 /* ext-family */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4145 switch (cpi->cpi_vendor) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4146 case X86_VENDOR_Intel:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4147 case X86_VENDOR_AMD:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4148 create = cpi->cpi_family >= 0xf;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4149 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4150 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4151 create = 0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4152 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4153 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4154 if (create)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4155 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4156 "ext-family", CPI_FAMILY_XTD(cpi));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4157
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4158 /* ext-model */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4159 switch (cpi->cpi_vendor) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4160 case X86_VENDOR_Intel:
6317 8afb524fc268 6667600 Incomplete initialization of cpi_cacheinfo field of struct cpuid_info kk208521 parents: 5870 diff changeset	4161 create = IS_EXTENDED_MODEL_INTEL(cpi);
2001 427a702b03e2 6427092 extended-model CPUID information is different between AMD and Intel dmick parents: 1975 diff changeset	4162 break;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4163 case X86_VENDOR_AMD:
1582 eb879d43ab47 6323525 Mutual exclusion primitives don't work as expected on Opteron systems kchow parents: 1414 diff changeset	4164 create = CPI_FAMILY(cpi) == 0xf;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4165 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4166 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4167 create = 0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4168 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4169 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4170 if (create)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4171 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	4172 "ext-model", CPI_MODEL_XTD(cpi));
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4173
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4174 /* generation */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4175 switch (cpi->cpi_vendor) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4176 case X86_VENDOR_AMD:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4177 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4178 * AMD K5 model 1 was the first part to support this
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4179 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4180 create = cpi->cpi_xmaxeax >= 0x80000001;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4181 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4182 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4183 create = 0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4184 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4185 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4186 if (create)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4187 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4188 "generation", BITX((cpi)->cpi_extd[1].cp_eax, 11, 8));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4189
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4190 /* brand-id */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4191 switch (cpi->cpi_vendor) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4192 case X86_VENDOR_Intel:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4193 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4194 * brand id first appeared on Pentium III Xeon model 8,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4195 * and Celeron model 8 processors and Opteron
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4196 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4197 create = cpi->cpi_family > 6 \|\|
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4198 (cpi->cpi_family == 6 && cpi->cpi_model >= 8);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4199 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4200 case X86_VENDOR_AMD:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4201 create = cpi->cpi_family >= 0xf;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4202 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4203 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4204 create = 0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4205 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4206 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4207 if (create && cpi->cpi_brandid != 0) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4208 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4209 "brand-id", cpi->cpi_brandid);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4210 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4211
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4212 /* chunks, and apic-id */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4213 switch (cpi->cpi_vendor) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4214 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4215 * first available on Pentium IV and Opteron (K8)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4216 */
1975 7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	4217 case X86_VENDOR_Intel:
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	4218 create = IS_NEW_F6(cpi) \|\| cpi->cpi_family >= 0xf;
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	4219 break;
7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	4220 case X86_VENDOR_AMD:
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4221 create = cpi->cpi_family >= 0xf;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4222 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4223 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4224 create = 0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4225 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4226 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4227 if (create) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4228 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	4229 "chunks", CPI_CHUNKS(cpi));
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4230 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
7282 5b3b6674ac91 6528768 apic_navail_vector() fails when IPL equals 8 or 9 mishra parents: 6964 diff changeset	4231 "apic-id", cpi->cpi_apicid);
1414 b4126407ac5b PSARC 2006/020 FMA for Athlon 64 and Opteron Processors cindi parents: 1228 diff changeset	4232 if (cpi->cpi_chipid >= 0) {
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4233 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4234 "chip#", cpi->cpi_chipid);
1414 b4126407ac5b PSARC 2006/020 FMA for Athlon 64 and Opteron Processors cindi parents: 1228 diff changeset	4235 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
b4126407ac5b PSARC 2006/020 FMA for Athlon 64 and Opteron Processors cindi parents: 1228 diff changeset	4236 "clog#", cpi->cpi_clogid);
b4126407ac5b PSARC 2006/020 FMA for Athlon 64 and Opteron Processors cindi parents: 1228 diff changeset	4237 }
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4238 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4239
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4240 /* cpuid-features */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4241 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4242 "cpuid-features", CPI_FEATURES_EDX(cpi));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4243
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4244
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4245 /* cpuid-features-ecx */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4246 switch (cpi->cpi_vendor) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4247 case X86_VENDOR_Intel:
1975 7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	4248 create = IS_NEW_F6(cpi) \|\| cpi->cpi_family >= 0xf;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4249 break;
13655 0461a7e94e53 2412 Various CPU features aren't intel specific Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13651 diff changeset	4250 case X86_VENDOR_AMD:
0461a7e94e53 2412 Various CPU features aren't intel specific Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13651 diff changeset	4251 create = cpi->cpi_family >= 0xf;
0461a7e94e53 2412 Various CPU features aren't intel specific Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> parents: 13651 diff changeset	4252 break;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4253 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4254 create = 0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4255 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4256 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4257 if (create)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4258 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4259 "cpuid-features-ecx", CPI_FEATURES_ECX(cpi));
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4260
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4261 /* ext-cpuid-features */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4262 switch (cpi->cpi_vendor) {
1975 7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	4263 case X86_VENDOR_Intel:
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4264 case X86_VENDOR_AMD:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4265 case X86_VENDOR_Cyrix:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4266 case X86_VENDOR_TM:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4267 case X86_VENDOR_Centaur:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4268 create = cpi->cpi_xmaxeax >= 0x80000001;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4269 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4270 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4271 create = 0;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4272 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4273 }
1975 7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	4274 if (create) {
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4275 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	4276 "ext-cpuid-features", CPI_FEATURES_XTD_EDX(cpi));
1975 7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	4277 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	4278 "ext-cpuid-features-ecx", CPI_FEATURES_XTD_ECX(cpi));
1975 7490b056500b 6183891 Missing brand ID strings for several common x86 CPUs dmick parents: 1727 diff changeset	4279 }
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4280
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4281 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4282 * Brand String first appeared in Intel Pentium IV, AMD K5
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4283 * model 1, and Cyrix GXm. On earlier models we try and
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4284 * simulate something similar .. so this string should always
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4285 * same -something- about the processor, however lame.
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4286 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4287 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi,
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4288 "brand-string", cpi->cpi_brandstr);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4289
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4290 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4291 * Finally, cache and tlb information
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4292 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4293 switch (x86_which_cacheinfo(cpi)) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4294 case X86_VENDOR_Intel:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4295 intel_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4296 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4297 case X86_VENDOR_Cyrix:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4298 cyrix_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4299 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4300 case X86_VENDOR_AMD:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4301 amd_cache_info(cpi, cpu_devi);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4302 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4303 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4304 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4305 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4306 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4307
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4308 struct l2info {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4309 int *l2i_csz;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4310 int *l2i_lsz;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4311 int *l2i_assoc;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4312 int l2i_ret;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4313 };
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4314
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4315 /*
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4316 * A cacheinfo walker that fetches the size, line-size and associativity
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4317 * of the L2 cache
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4318 */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4319 static int
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4320 intel_l2cinfo(void arg, const struct cachetab ct)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4321 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4322 struct l2info *l2i = arg;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4323 int *ip;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4324
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4325 if (ct->ct_label != l2_cache_str &&
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4326 ct->ct_label != sl2_cache_str)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4327 return (0); /* not an L2 -- keep walking */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4328
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4329 if ((ip = l2i->l2i_csz) != NULL)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4330 *ip = ct->ct_size;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4331 if ((ip = l2i->l2i_lsz) != NULL)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4332 *ip = ct->ct_line_size;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4333 if ((ip = l2i->l2i_assoc) != NULL)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4334 *ip = ct->ct_assoc;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4335 l2i->l2i_ret = ct->ct_size;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4336 return (1); /* was an L2 -- terminate walk */
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4337 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4338
5070 f1c8fa0cbaca 6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system kchow parents: 5045 diff changeset	4339 /*
f1c8fa0cbaca 6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system kchow parents: 5045 diff changeset	4340 * AMD L2/L3 Cache and TLB Associativity Field Definition:
f1c8fa0cbaca 6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system kchow parents: 5045 diff changeset	4341 *
f1c8fa0cbaca 6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system kchow parents: 5045 diff changeset	4342 * Unlike the associativity for the L1 cache and tlb where the 8 bit
f1c8fa0cbaca 6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system kchow parents: 5045 diff changeset	4343 * value is the associativity, the associativity for the L2 cache and
f1c8fa0cbaca 6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system kchow parents: 5045 diff changeset	4344 * tlb is encoded in the following table. The 4 bit L2 value serves as
f1c8fa0cbaca 6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system kchow parents: 5045 diff changeset	4345 * an index into the amd_afd[] array to determine the associativity.
f1c8fa0cbaca 6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system kchow parents: 5045 diff changeset	4346 * -1 is undefined. 0 is fully associative.
f1c8fa0cbaca 6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system kchow parents: 5045 diff changeset	4347 */
f1c8fa0cbaca 6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system kchow parents: 5045 diff changeset	4348
f1c8fa0cbaca 6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system kchow parents: 5045 diff changeset	4349 static int amd_afd[] =
f1c8fa0cbaca 6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system kchow parents: 5045 diff changeset	4350 {-1, 1, 2, -1, 4, -1, 8, -1, 16, -1, 32, 48, 64, 96, 128, 0};
f1c8fa0cbaca 6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system kchow parents: 5045 diff changeset	4351
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4352 static void
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4353 amd_l2cacheinfo(struct cpuid_info cpi, struct l2info l2i)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4354 {
1228 9e051e1a3f68 6282049 CMT update needed for x86 CPU detection andrei parents: 938 diff changeset	4355 struct cpuid_regs *cp;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4356 uint_t size, assoc;
5070 f1c8fa0cbaca 6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system kchow parents: 5045 diff changeset	4357 int i;
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4358 int *ip;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4359
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4360 if (cpi->cpi_xmaxeax < 0x80000006)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4361 return;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4362 cp = &cpi->cpi_extd[6];
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4363
5070 f1c8fa0cbaca 6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system kchow parents: 5045 diff changeset	4364 if ((i = BITX(cp->cp_ecx, 15, 12)) != 0 &&
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4365 (size = BITX(cp->cp_ecx, 31, 16)) != 0) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4366 uint_t cachesz = size * 1024;
5070 f1c8fa0cbaca 6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system kchow parents: 5045 diff changeset	4367 assoc = amd_afd[i];
f1c8fa0cbaca 6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system kchow parents: 5045 diff changeset	4368
f1c8fa0cbaca 6580117 panic: assertion failed: ISP2(CPUSETSIZE()) on VIA Esther based system kchow parents: 5045 diff changeset	4369 ASSERT(assoc != -1);
0 68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4370
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4371 if ((ip = l2i->l2i_csz) != NULL)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4372 *ip = cachesz;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4373 if ((ip = l2i->l2i_lsz) != NULL)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4374 *ip = BITX(cp->cp_ecx, 7, 0);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4375 if ((ip = l2i->l2i_assoc) != NULL)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4376 *ip = assoc;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4377 l2i->l2i_ret = cachesz;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4378 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4379 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4380
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4381 int
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4382 getl2cacheinfo(cpu_t cpu, int csz, int lsz, int assoc)
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4383 {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4384 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4385 struct l2info __l2info, *l2i = &__l2info;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4386
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4387 l2i->l2i_csz = csz;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4388 l2i->l2i_lsz = lsz;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4389 l2i->l2i_assoc = assoc;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4390 l2i->l2i_ret = -1;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4391
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4392 switch (x86_which_cacheinfo(cpi)) {
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4393 case X86_VENDOR_Intel:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4394 intel_walk_cacheinfo(cpi, l2i, intel_l2cinfo);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4395 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4396 case X86_VENDOR_Cyrix:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4397 cyrix_walk_cacheinfo(cpi, l2i, intel_l2cinfo);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4398 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4399 case X86_VENDOR_AMD:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4400 amd_l2cacheinfo(cpi, l2i);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4401 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4402 default:
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4403 break;
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4404 }
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4405 return (l2i->l2i_ret);
68f95e015346 OpenSolaris Launch stevel@tonic-gate parents: diff changeset	4406 }
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	4407
5084 7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	4408 #if !defined(__xpv)
7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	4409
5045 75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4410 uint32_t *
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4411 cpuid_mwait_alloc(cpu_t *cpu)
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4412 {
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4413 uint32_t *ret;
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4414 size_t mwait_size;
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4415
12004 93f274d4a367 PSARC/2009/104 Hot-Plug Support for ACPI-based Systems Gerry Liu <jiang.liu@intel.com> parents: 11919 diff changeset	4416 ASSERT(cpuid_checkpass(CPU, 2));
93f274d4a367 PSARC/2009/104 Hot-Plug Support for ACPI-based Systems Gerry Liu <jiang.liu@intel.com> parents: 11919 diff changeset	4417
93f274d4a367 PSARC/2009/104 Hot-Plug Support for ACPI-based Systems Gerry Liu <jiang.liu@intel.com> parents: 11919 diff changeset	4418 mwait_size = CPU->cpu_m.mcpu_cpi->cpi_mwait.mon_max;
5045 75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4419 if (mwait_size == 0)
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4420 return (NULL);
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4421
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4422 /*
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4423 * kmem_alloc() returns cache line size aligned data for mwait_size
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4424 * allocations. mwait_size is currently cache line sized. Neither
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4425 * of these implementation details are guarantied to be true in the
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4426 * future.
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4427 *
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4428 * First try allocating mwait_size as kmem_alloc() currently returns
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4429 * correctly aligned memory. If kmem_alloc() does not return
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4430 * mwait_size aligned memory, then use mwait_size ROUNDUP.
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4431 *
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4432 * Set cpi_mwait.buf_actual and cpi_mwait.size_actual in case we
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4433 * decide to free this memory.
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4434 */
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4435 ret = kmem_zalloc(mwait_size, KM_SLEEP);
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4436 if (ret == (uint32_t *)P2ROUNDUP((uintptr_t)ret, mwait_size)) {
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4437 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = ret;
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4438 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = mwait_size;
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4439 *ret = MWAIT_RUNNING;
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4440 return (ret);
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4441 } else {
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4442 kmem_free(ret, mwait_size);
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4443 ret = kmem_zalloc(mwait_size * 2, KM_SLEEP);
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4444 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = ret;
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4445 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = mwait_size * 2;
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4446 ret = (uint32_t *)P2ROUNDUP((uintptr_t)ret, mwait_size);
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4447 *ret = MWAIT_RUNNING;
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4448 return (ret);
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4449 }
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4450 }
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4451
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4452 void
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4453 cpuid_mwait_free(cpu_t *cpu)
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	4454 {
12004 93f274d4a367 PSARC/2009/104 Hot-Plug Support for ACPI-based Systems Gerry Liu <jiang.liu@intel.com> parents: 11919 diff changeset	4455 if (cpu->cpu_m.mcpu_cpi == NULL) {
93f274d4a367 PSARC/2009/104 Hot-Plug Support for ACPI-based Systems Gerry Liu <jiang.liu@intel.com> parents: 11919 diff changeset	4456 return;
93f274d4a367 PSARC/2009/104 Hot-Plug Support for ACPI-based Systems Gerry Liu <jiang.liu@intel.com> parents: 11919 diff changeset	4457 }
5045 75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4458
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4459 if (cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual != NULL &&
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4460 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual > 0) {
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4461 kmem_free(cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual,
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4462 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual);
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4463 }
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4464
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4465 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = NULL;
75a798a98460 6577948 mach_alloc_mwait leaks memory when a CPU fails to start bholler parents: 4858 diff changeset	4466 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = 0;
4481 2bb321aaf3c3 6495392 use monitor/mwait for halting idle CPUs where supported bholler parents: 4265 diff changeset	4467 }
5084 7d838c5c0eed PSARC 2006/260 Solaris on Xen johnlev parents: 5070 diff changeset	4468
5322 010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4469 void
010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4470 patch_tsc_read(int flag)
010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4471 {
010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4472 size_t cnt;
7532 bb6372f778bb PSARC 2008/569 FMA Topology & Retire Agent Refinements Cheng Sean Ye <Sean.Ye@Sun.COM> parents: 7282 diff changeset	4473
5322 010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4474 switch (flag) {
010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4475 case X86_NO_TSC:
010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4476 cnt = &_no_rdtsc_end - &_no_rdtsc_start;
5338 fd7cad8433cf 6600939 gethrtime sometimes return a large time value into the future (fix lint) sudheer parents: 5322 diff changeset	4477 (void) memcpy((void )tsc_read, (void )&_no_rdtsc_start, cnt);
5322 010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4478 break;
010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4479 case X86_HAVE_TSCP:
010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4480 cnt = &_tscp_end - &_tscp_start;
5338 fd7cad8433cf 6600939 gethrtime sometimes return a large time value into the future (fix lint) sudheer parents: 5322 diff changeset	4481 (void) memcpy((void )tsc_read, (void )&_tscp_start, cnt);
5322 010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4482 break;
010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4483 case X86_TSC_MFENCE:
010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4484 cnt = &_tsc_mfence_end - &_tsc_mfence_start;
5338 fd7cad8433cf 6600939 gethrtime sometimes return a large time value into the future (fix lint) sudheer parents: 5322 diff changeset	4485 (void) memcpy((void *)tsc_read,
fd7cad8433cf 6600939 gethrtime sometimes return a large time value into the future (fix lint) sudheer parents: 5322 diff changeset	4486 (void *)&_tsc_mfence_start, cnt);
5322 010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4487 break;
6642 c41a8f6eba0e 6671782 rdtsc synchronization change for Intel processors sudheer parents: 6445 diff changeset	4488 case X86_TSC_LFENCE:
c41a8f6eba0e 6671782 rdtsc synchronization change for Intel processors sudheer parents: 6445 diff changeset	4489 cnt = &_tsc_lfence_end - &_tsc_lfence_start;
c41a8f6eba0e 6671782 rdtsc synchronization change for Intel processors sudheer parents: 6445 diff changeset	4490 (void) memcpy((void *)tsc_read,
c41a8f6eba0e 6671782 rdtsc synchronization change for Intel processors sudheer parents: 6445 diff changeset	4491 (void *)&_tsc_lfence_start, cnt);
c41a8f6eba0e 6671782 rdtsc synchronization change for Intel processors sudheer parents: 6445 diff changeset	4492 break;
5322 010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4493 default:
010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4494 break;
010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4495 }
010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4496 }
010e79fdab36 6600939 gethrtime sometimes return a large time value into the future sudheer parents: 5284 diff changeset	4497
8906 e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4498 int
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4499 cpuid_deep_cstates_supported(void)
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4500 {
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4501 struct cpuid_info *cpi;
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4502 struct cpuid_regs regs;
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4503
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4504 ASSERT(cpuid_checkpass(CPU, 1));
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4505
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4506 cpi = CPU->cpu_m.mcpu_cpi;
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4507
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	4508 if (!is_x86_feature(x86_featureset, X86FSET_CPUID))
8906 e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4509 return (0);
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4510
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4511 switch (cpi->cpi_vendor) {
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4512 case X86_VENDOR_Intel:
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4513 if (cpi->cpi_xmaxeax < 0x80000007)
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4514 return (0);
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4515
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4516 /*
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4517 * TSC run at a constant rate in all ACPI C-states?
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4518 */
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4519 regs.cp_eax = 0x80000007;
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4520 (void) __cpuid_insn(&regs);
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4521 return (regs.cp_edx & CPUID_TSC_CSTATE_INVARIANCE);
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4522
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4523 default:
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4524 return (0);
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4525 }
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4526 }
e559381f1e2b PSARC 2008/777 cpupm keyword mode extensions Eric Saxe <Eric.Saxe@Sun.COM> parents: 8418 diff changeset	4527
8930 02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4528 #endif /* !__xpv */
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4529
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4530 void
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4531 post_startup_cpu_fixups(void)
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4532 {
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4533 #ifndef __xpv
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4534 /*
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4535 * Some AMD processors support C1E state. Entering this state will
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4536 * cause the local APIC timer to stop, which we can't deal with at
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4537 * this time.
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4538 */
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4539 if (cpuid_getvendor(CPU) == X86_VENDOR_AMD) {
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4540 on_trap_data_t otd;
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4541 uint64_t reg;
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4542
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4543 if (!on_trap(&otd, OT_DATA_ACCESS)) {
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4544 reg = rdmsr(MSR_AMD_INT_PENDING_CMP_HALT);
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4545 /* Disable C1E state if it is enabled by BIOS */
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4546 if ((reg >> AMD_ACTONCMPHALT_SHIFT) &
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4547 AMD_ACTONCMPHALT_MASK) {
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4548 reg &= ~(AMD_ACTONCMPHALT_MASK <<
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4549 AMD_ACTONCMPHALT_SHIFT);
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4550 wrmsr(MSR_AMD_INT_PENDING_CMP_HALT, reg);
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4551 }
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4552 }
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4553 no_trap();
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4554 }
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4555 #endif /* !__xpv */
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4556 }
02055889c73a 6786943 AMD-based systems with C1E state enabled hang at boot Bill Holler <Bill.Holler@Sun.COM> parents: 8906 diff changeset	4557
9283 2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4558 /*
13146 8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	4559 * Setup necessary registers to enable XSAVE feature on this processor.
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	4560 * This function needs to be called early enough, so that no xsave/xrstor
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	4561 * ops will execute on the processor before the MSRs are properly set up.
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	4562 *
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	4563 * Current implementation has the following assumption:
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	4564 * - cpuid_pass1() is done, so that X86 features are known.
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	4565 * - fpu_probe() is done, so that fp_save_mech is chosen.
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	4566 */
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	4567 void
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	4568 xsave_setup_msr(cpu_t *cpu)
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	4569 {
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	4570 ASSERT(fp_save_mech == FP_XSAVE);
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	4571 ASSERT(is_x86_feature(x86_featureset, X86FSET_XSAVE));
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	4572
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	4573 /* Enable OSXSAVE in CR4. */
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	4574 setcr4(getcr4() \| CR4_OSXSAVE);
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	4575 /*
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	4576 * Update SW copy of ECX, so that /dev/cpu/self/cpuid will report
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	4577 * correct value.
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	4578 */
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	4579 cpu->cpu_m.mcpu_cpi->cpi_std[1].cp_ecx \|= CPUID_INTC_ECX_OSXSAVE;
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	4580 setup_xfem();
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	4581 }
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	4582
8315ff49e22e 6958308 XSAVE/XRSTOR mechanism to save and restore processor state Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 13041 diff changeset	4583 /*
9283 2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4584 * Starting with the Westmere processor the local
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4585 * APIC timer will continue running in all C-states,
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4586 * including the deepest C-states.
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4587 */
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4588 int
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4589 cpuid_arat_supported(void)
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4590 {
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4591 struct cpuid_info *cpi;
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4592 struct cpuid_regs regs;
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4593
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4594 ASSERT(cpuid_checkpass(CPU, 1));
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	4595 ASSERT(is_x86_feature(x86_featureset, X86FSET_CPUID));
9283 2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4596
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4597 cpi = CPU->cpu_m.mcpu_cpi;
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4598
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4599 switch (cpi->cpi_vendor) {
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4600 case X86_VENDOR_Intel:
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4601 /*
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4602 * Always-running Local APIC Timer is
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4603 * indicated by CPUID.6.EAX[2].
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4604 */
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4605 if (cpi->cpi_maxeax >= 6) {
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4606 regs.cp_eax = 6;
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4607 (void) cpuid_insn(NULL, &regs);
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4608 return (regs.cp_eax & CPUID_CSTATE_ARAT);
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4609 } else {
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4610 return (0);
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4611 }
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4612 default:
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4613 return (0);
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4614 }
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4615 }
2ee48b3d20ef 6821708 deeper C-state support required for processors with ARAT Bill Holler <Bill.Holler@Sun.COM> parents: 9000 diff changeset	4616
10992 54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4617 /*
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4618 * Check support for Intel ENERGY_PERF_BIAS feature
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4619 */
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4620 int
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4621 cpuid_iepb_supported(struct cpu *cp)
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4622 {
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4623 struct cpuid_info *cpi = cp->cpu_m.mcpu_cpi;
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4624 struct cpuid_regs regs;
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4625
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4626 ASSERT(cpuid_checkpass(cp, 1));
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4627
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	4628 if (!(is_x86_feature(x86_featureset, X86FSET_CPUID)) \|\|
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	4629 !(is_x86_feature(x86_featureset, X86FSET_MSR))) {
10992 54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4630 return (0);
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4631 }
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4632
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4633 /*
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4634 * Intel ENERGY_PERF_BIAS MSR is indicated by
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4635 * capability bit CPUID.6.ECX.3
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4636 */
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4637 if ((cpi->cpi_vendor != X86_VENDOR_Intel) \|\| (cpi->cpi_maxeax < 6))
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4638 return (0);
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4639
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4640 regs.cp_eax = 0x6;
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4641 (void) cpuid_insn(NULL, &regs);
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4642 return (regs.cp_ecx & CPUID_EPB_SUPPORT);
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4643 }
54a1c1cbd683 6887944 support for IA32_ENERGY_PERF_BIAS MSR aubrey.li@intel.com parents: 10947 diff changeset	4644
13041 2ba2eec82e2a 6932990 Support for TSC deadline timer Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM> parents: 12838 diff changeset	4645 /*
2ba2eec82e2a 6932990 Support for TSC deadline timer Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM> parents: 12838 diff changeset	4646 * Check support for TSC deadline timer
2ba2eec82e2a 6932990 Support for TSC deadline timer Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM> parents: 12838 diff changeset	4647 *
2ba2eec82e2a 6932990 Support for TSC deadline timer Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM> parents: 12838 diff changeset	4648 * TSC deadline timer provides a superior software programming
2ba2eec82e2a 6932990 Support for TSC deadline timer Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM> parents: 12838 diff changeset	4649 * model over local APIC timer that eliminates "time drifts".
2ba2eec82e2a 6932990 Support for TSC deadline timer Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM> parents: 12838 diff changeset	4650 * Instead of specifying a relative time, software specifies an
2ba2eec82e2a 6932990 Support for TSC deadline timer Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM> parents: 12838 diff changeset	4651 * absolute time as the target at which the processor should
2ba2eec82e2a 6932990 Support for TSC deadline timer Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM> parents: 12838 diff changeset	4652 * generate a timer event.
2ba2eec82e2a 6932990 Support for TSC deadline timer Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM> parents: 12838 diff changeset	4653 */
2ba2eec82e2a 6932990 Support for TSC deadline timer Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM> parents: 12838 diff changeset	4654 int
2ba2eec82e2a 6932990 Support for TSC deadline timer Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM> parents: 12838 diff changeset	4655 cpuid_deadline_tsc_supported(void)
2ba2eec82e2a 6932990 Support for TSC deadline timer Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM> parents: 12838 diff changeset	4656 {
2ba2eec82e2a 6932990 Support for TSC deadline timer Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM> parents: 12838 diff changeset	4657 struct cpuid_info *cpi = CPU->cpu_m.mcpu_cpi;
2ba2eec82e2a 6932990 Support for TSC deadline timer Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM> parents: 12838 diff changeset	4658 struct cpuid_regs regs;
2ba2eec82e2a 6932990 Support for TSC deadline timer Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM> parents: 12838 diff changeset	4659
2ba2eec82e2a 6932990 Support for TSC deadline timer Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM> parents: 12838 diff changeset	4660 ASSERT(cpuid_checkpass(CPU, 1));
2ba2eec82e2a 6932990 Support for TSC deadline timer Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM> parents: 12838 diff changeset	4661 ASSERT(is_x86_feature(x86_featureset, X86FSET_CPUID));
2ba2eec82e2a 6932990 Support for TSC deadline timer Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM> parents: 12838 diff changeset	4662
2ba2eec82e2a 6932990 Support for TSC deadline timer Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM> parents: 12838 diff changeset	4663 switch (cpi->cpi_vendor) {
2ba2eec82e2a 6932990 Support for TSC deadline timer Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM> parents: 12838 diff changeset	4664 case X86_VENDOR_Intel:
2ba2eec82e2a 6932990 Support for TSC deadline timer Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM> parents: 12838 diff changeset	4665 if (cpi->cpi_maxeax >= 1) {
2ba2eec82e2a 6932990 Support for TSC deadline timer Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM> parents: 12838 diff changeset	4666 regs.cp_eax = 1;
2ba2eec82e2a 6932990 Support for TSC deadline timer Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM> parents: 12838 diff changeset	4667 (void) cpuid_insn(NULL, &regs);
2ba2eec82e2a 6932990 Support for TSC deadline timer Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM> parents: 12838 diff changeset	4668 return (regs.cp_ecx & CPUID_DEADLINE_TSC);
2ba2eec82e2a 6932990 Support for TSC deadline timer Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM> parents: 12838 diff changeset	4669 } else {
2ba2eec82e2a 6932990 Support for TSC deadline timer Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM> parents: 12838 diff changeset	4670 return (0);
2ba2eec82e2a 6932990 Support for TSC deadline timer Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM> parents: 12838 diff changeset	4671 }
2ba2eec82e2a 6932990 Support for TSC deadline timer Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM> parents: 12838 diff changeset	4672 default:
2ba2eec82e2a 6932990 Support for TSC deadline timer Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM> parents: 12838 diff changeset	4673 return (0);
2ba2eec82e2a 6932990 Support for TSC deadline timer Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM> parents: 12838 diff changeset	4674 }
2ba2eec82e2a 6932990 Support for TSC deadline timer Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM> parents: 12838 diff changeset	4675 }
2ba2eec82e2a 6932990 Support for TSC deadline timer Krishnendu Sadhukhan - Sun Microsystems <Krishnendu.Sadhukhan@Sun.COM> parents: 12838 diff changeset	4676
8377 e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4677 #if defined(__amd64) && !defined(__xpv)
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4678 /*
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4679 * Patch in versions of bcopy for high performance Intel Nhm processors
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4680 * and later...
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4681 */
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4682 void
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4683 patch_memops(uint_t vendor)
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4684 {
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4685 size_t cnt, i;
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4686 caddr_t to, from;
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4687
12838 fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	4688 if ((vendor == X86_VENDOR_Intel) &&
fca99d9e3f2f 6812663 Running out of bits in x86_feature Kuriakose Kuruvilla <kuriakose.kuruvilla@oracle.com> parents: 12726 diff changeset	4689 is_x86_feature(x86_featureset, X86FSET_SSE4_2)) {
8377 e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4690 cnt = &bcopy_patch_end - &bcopy_patch_start;
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4691 to = &bcopy_ck_size;
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4692 from = &bcopy_patch_start;
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4693 for (i = 0; i < cnt; i++) {
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4694 to++ = from++;
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4695 }
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4696 }
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4697 }
e4fb59d35f38 6292199 bcopy and kcopy should'nt use rep, smov Bill Holler <Bill.Holler@Sun.COM> parents: 7798 diff changeset	4698 #endif /* __amd64 && !__xpv */
12261 52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4699
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4700 /*
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4701 * This function finds the number of bits to represent the number of cores per
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4702 * chip and the number of strands per core for the Intel platforms.
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4703 * It re-uses the x2APIC cpuid code of the cpuid_pass2().
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4704 */
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4705 void
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4706 cpuid_get_ext_topo(uint_t vendor, uint_t core_nbits, uint_t strand_nbits)
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4707 {
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4708 struct cpuid_regs regs;
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4709 struct cpuid_regs *cp = &regs;
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4710
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4711 if (vendor != X86_VENDOR_Intel) {
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4712 return;
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4713 }
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4714
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4715 /* if the cpuid level is 0xB, extended topo is available. */
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4716 cp->cp_eax = 0;
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4717 if (__cpuid_insn(cp) >= 0xB) {
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4718
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4719 cp->cp_eax = 0xB;
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4720 cp->cp_edx = cp->cp_ebx = cp->cp_ecx = 0;
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4721 (void) __cpuid_insn(cp);
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4722
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4723 /*
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4724 * Check CPUID.EAX=0BH, ECX=0H:EBX is non-zero, which
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4725 * indicates that the extended topology enumeration leaf is
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4726 * available.
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4727 */
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4728 if (cp->cp_ebx) {
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4729 uint_t coreid_shift = 0;
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4730 uint_t chipid_shift = 0;
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4731 uint_t i;
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4732 uint_t level;
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4733
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4734 for (i = 0; i < CPI_FNB_ECX_MAX; i++) {
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4735 cp->cp_eax = 0xB;
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4736 cp->cp_ecx = i;
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4737
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4738 (void) __cpuid_insn(cp);
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4739 level = CPI_CPU_LEVEL_TYPE(cp);
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4740
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4741 if (level == 1) {
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4742 /*
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4743 * Thread level processor topology
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4744 * Number of bits shift right APIC ID
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4745 * to get the coreid.
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4746 */
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4747 coreid_shift = BITX(cp->cp_eax, 4, 0);
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4748 } else if (level == 2) {
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4749 /*
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4750 * Core level processor topology
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4751 * Number of bits shift right APIC ID
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4752 * to get the chipid.
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4753 */
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4754 chipid_shift = BITX(cp->cp_eax, 4, 0);
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4755 }
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4756 }
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4757
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4758 if (coreid_shift > 0 && chipid_shift > coreid_shift) {
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4759 *strand_nbits = coreid_shift;
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4760 *core_nbits = chipid_shift - coreid_shift;
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4761 }
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4762 }
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4763 }
52117d41c06e 6930914 Need enhancement of the cmi handle table for Intel EX chip family Vuong Nguyen <Vuong.Nguyen@Sun.COM> parents: 12090 diff changeset	4764 }

Mercurial > illumos > illumos-gate

annotate usr/src/uts/i86pc/os/cpuid.c @ 14043:0291cd939b43